1 /* 2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 3 * 4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _CONFIG_EB_CPU5282_H_ 10 #define _CONFIG_EB_CPU5282_H_ 11 12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 13 14 /*----------------------------------------------------------------------* 15 * High Level Configuration Options (easy to change) * 16 *----------------------------------------------------------------------*/ 17 18 #define CONFIG_MISC_INIT_R 19 20 #define CONFIG_MCFUART 21 #define CONFIG_SYS_UART_PORT (0) 22 23 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 24 25 #define CONFIG_BOOTCOMMAND "printenv" 26 27 /*----------------------------------------------------------------------* 28 * Options * 29 *----------------------------------------------------------------------*/ 30 31 #define CONFIG_BOOT_RETRY_TIME -1 32 #define CONFIG_RESET_TO_RETRY 33 #define CONFIG_SPLASH_SCREEN 34 35 #define CONFIG_HW_WATCHDOG 36 37 #define STATUS_LED_ACTIVE 0 38 39 /*----------------------------------------------------------------------* 40 * Configuration for environment * 41 * Environment is in the second sector of the first 256k of flash * 42 *----------------------------------------------------------------------*/ 43 44 #define CONFIG_ENV_ADDR 0xFF040000 45 #define CONFIG_ENV_SECT_SIZE 0x00020000 46 47 /* 48 * BOOTP options 49 */ 50 #define CONFIG_BOOTP_BOOTFILESIZE 51 #define CONFIG_BOOTP_BOOTPATH 52 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_HOSTNAME 54 55 /* 56 * Command line configuration. 57 */ 58 #define CONFIG_CMDLINE_EDITING 59 60 #define CONFIG_MCFTMR 61 62 #define CONFIG_SYS_LONGHELP 1 63 64 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 65 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 66 67 #define CONFIG_SYS_LOAD_ADDR 0x20000 68 69 #define CONFIG_SYS_MEMTEST_START 0x100000 70 #define CONFIG_SYS_MEMTEST_END 0x400000 71 /*#define CONFIG_SYS_DRAM_TEST 1 */ 72 #undef CONFIG_SYS_DRAM_TEST 73 74 /*----------------------------------------------------------------------* 75 * Clock and PLL Configuration * 76 *----------------------------------------------------------------------*/ 77 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 78 79 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 80 81 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 82 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 83 84 /*----------------------------------------------------------------------* 85 * Network * 86 *----------------------------------------------------------------------*/ 87 88 #define CONFIG_MCFFEC 89 #define CONFIG_MII 1 90 #define CONFIG_MII_INIT 1 91 #define CONFIG_SYS_DISCOVER_PHY 92 #define CONFIG_SYS_RX_ETH_BUFFER 8 93 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 94 95 #define CONFIG_SYS_FEC0_PINMUX 0 96 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 97 #define MCFFEC_TOUT_LOOP 50000 98 99 #define CONFIG_OVERWRITE_ETHADDR_ONCE 100 101 /*------------------------------------------------------------------------- 102 * Low Level Configuration Settings 103 * (address mappings, register initial values, etc.) 104 * You should know what you are doing if you make changes here. 105 *-----------------------------------------------------------------------*/ 106 107 #define CONFIG_SYS_MBAR 0x40000000 108 109 /*----------------------------------------------------------------------- 110 * Definitions for initial stack pointer and data area (in DPRAM) 111 *-----------------------------------------------------------------------*/ 112 113 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 114 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 115 #define CONFIG_SYS_GBL_DATA_OFFSET \ 116 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 117 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 118 119 /*----------------------------------------------------------------------- 120 * Start addresses for the final memory configuration 121 * (Set up by the startup code) 122 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 123 */ 124 #define CONFIG_SYS_SDRAM_BASE0 0x00000000 125 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 126 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 128 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 129 130 #define CONFIG_SYS_MONITOR_LEN 0x20000 131 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 132 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 133 134 /* 135 * For booting Linux, the board info and command line data 136 * have to be in the first 8 MB of memory, since this is 137 * the maximum mapped by the Linux kernel during initialization ?? 138 */ 139 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 140 141 /*----------------------------------------------------------------------- 142 * FLASH organization 143 */ 144 #define CONFIG_FLASH_SHOW_PROGRESS 45 145 146 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 147 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 148 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 149 150 #define CONFIG_SYS_MAX_FLASH_SECT 128 151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 152 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 153 #define CONFIG_SYS_FLASH_PROTECTION 154 155 #define CONFIG_SYS_FLASH_CFI 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 158 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 159 160 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 161 162 /*----------------------------------------------------------------------- 163 * Cache Configuration 164 */ 165 #define CONFIG_SYS_CACHELINE_SIZE 16 166 167 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 168 CONFIG_SYS_INIT_RAM_SIZE - 8) 169 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 170 CONFIG_SYS_INIT_RAM_SIZE - 4) 171 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 172 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 174 CF_ACR_EN | CF_ACR_SM_ALL) 175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 176 CF_CACR_CEIB | CF_CACR_DBWE | \ 177 CF_CACR_EUSP) 178 179 /*----------------------------------------------------------------------- 180 * Memory bank definitions 181 */ 182 183 #define CONFIG_SYS_CS0_BASE 0xFF000000 184 #define CONFIG_SYS_CS0_CTRL 0x00001980 185 #define CONFIG_SYS_CS0_MASK 0x00FF0001 186 187 #define CONFIG_SYS_CS2_BASE 0xE0000000 188 #define CONFIG_SYS_CS2_CTRL 0x00001980 189 #define CONFIG_SYS_CS2_MASK 0x000F0001 190 191 #define CONFIG_SYS_CS3_BASE 0xE0100000 192 #define CONFIG_SYS_CS3_CTRL 0x00001980 193 #define CONFIG_SYS_CS3_MASK 0x000F0001 194 195 /*----------------------------------------------------------------------- 196 * Port configuration 197 */ 198 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 199 #define CONFIG_SYS_PADDR 0x0000000 200 #define CONFIG_SYS_PADAT 0x0000000 201 202 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 203 #define CONFIG_SYS_PBDDR 0x0000000 204 #define CONFIG_SYS_PBDAT 0x0000000 205 206 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 207 #define CONFIG_SYS_PCDDR 0x0000000 208 #define CONFIG_SYS_PCDAT 0x0000000 209 210 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 211 #define CONFIG_SYS_PCDDR 0x0000000 212 #define CONFIG_SYS_PCDAT 0x0000000 213 214 #define CONFIG_SYS_PASPAR 0x0F0F 215 #define CONFIG_SYS_PEHLPAR 0xC0 216 #define CONFIG_SYS_PUAPAR 0x0F 217 #define CONFIG_SYS_DDRUA 0x05 218 #define CONFIG_SYS_PJPAR 0xFF 219 220 /*----------------------------------------------------------------------- 221 * I2C 222 */ 223 224 #define CONFIG_SYS_I2C 225 #define CONFIG_SYS_I2C_FSL 226 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 228 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 229 230 #define CONFIG_SYS_FSL_I2C_SPEED 100000 231 #define CONFIG_SYS_FSL_I2C_SLAVE 0 232 233 #ifdef CONFIG_CMD_DATE 234 #define CONFIG_RTC_DS1338 235 #define CONFIG_I2C_RTC_ADDR 0x68 236 #endif 237 238 /*----------------------------------------------------------------------- 239 * VIDEO configuration 240 */ 241 242 #ifdef CONFIG_VIDEO 243 #define CONFIG_VIDEO_VCXK 1 244 245 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 246 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 247 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 248 249 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 250 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 251 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 252 253 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 254 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 255 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 256 257 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 258 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 259 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 260 261 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 262 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 263 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 264 265 #endif /* CONFIG_VIDEO */ 266 #endif /* _CONFIG_M5282EVB_H */ 267 /*---------------------------------------------------------------------*/ 268