1 /* 2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 3 * 4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _CONFIG_EB_CPU5282_H_ 10 #define _CONFIG_EB_CPU5282_H_ 11 12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 13 14 /*----------------------------------------------------------------------* 15 * High Level Configuration Options (easy to change) * 16 *----------------------------------------------------------------------*/ 17 18 #define CONFIG_MISC_INIT_R 19 20 #define CONFIG_MCFUART 21 #define CONFIG_SYS_UART_PORT (0) 22 #define CONFIG_BAUDRATE 115200 23 24 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 25 26 #define CONFIG_BOOTCOMMAND "printenv" 27 28 /*----------------------------------------------------------------------* 29 * Options * 30 *----------------------------------------------------------------------*/ 31 32 #define CONFIG_BOOT_RETRY_TIME -1 33 #define CONFIG_RESET_TO_RETRY 34 #define CONFIG_SPLASH_SCREEN 35 36 #define CONFIG_HW_WATCHDOG 37 38 #define STATUS_LED_ACTIVE 0 39 40 /*----------------------------------------------------------------------* 41 * Configuration for environment * 42 * Environment is in the second sector of the first 256k of flash * 43 *----------------------------------------------------------------------*/ 44 45 #define CONFIG_ENV_ADDR 0xFF040000 46 #define CONFIG_ENV_SECT_SIZE 0x00020000 47 #define CONFIG_ENV_IS_IN_FLASH 1 48 49 /* 50 * BOOTP options 51 */ 52 #define CONFIG_BOOTP_BOOTFILESIZE 53 #define CONFIG_BOOTP_BOOTPATH 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_HOSTNAME 56 57 /* 58 * Command line configuration. 59 */ 60 #define CONFIG_CMDLINE_EDITING 61 #define CONFIG_CMD_DATE 62 63 #define CONFIG_MCFTMR 64 65 #define CONFIG_SYS_LONGHELP 1 66 67 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 68 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 69 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 70 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 71 72 #define CONFIG_SYS_LOAD_ADDR 0x20000 73 74 #define CONFIG_SYS_MEMTEST_START 0x100000 75 #define CONFIG_SYS_MEMTEST_END 0x400000 76 /*#define CONFIG_SYS_DRAM_TEST 1 */ 77 #undef CONFIG_SYS_DRAM_TEST 78 79 /*----------------------------------------------------------------------* 80 * Clock and PLL Configuration * 81 *----------------------------------------------------------------------*/ 82 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 83 84 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 85 86 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 87 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 88 89 /*----------------------------------------------------------------------* 90 * Network * 91 *----------------------------------------------------------------------*/ 92 93 #define CONFIG_MCFFEC 94 #define CONFIG_MII 1 95 #define CONFIG_MII_INIT 1 96 #define CONFIG_SYS_DISCOVER_PHY 97 #define CONFIG_SYS_RX_ETH_BUFFER 8 98 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 99 100 #define CONFIG_SYS_FEC0_PINMUX 0 101 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 102 #define MCFFEC_TOUT_LOOP 50000 103 104 #define CONFIG_OVERWRITE_ETHADDR_ONCE 105 106 /*------------------------------------------------------------------------- 107 * Low Level Configuration Settings 108 * (address mappings, register initial values, etc.) 109 * You should know what you are doing if you make changes here. 110 *-----------------------------------------------------------------------*/ 111 112 #define CONFIG_SYS_MBAR 0x40000000 113 114 /*----------------------------------------------------------------------- 115 * Definitions for initial stack pointer and data area (in DPRAM) 116 *-----------------------------------------------------------------------*/ 117 118 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 119 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 120 #define CONFIG_SYS_GBL_DATA_OFFSET \ 121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 122 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 123 124 /*----------------------------------------------------------------------- 125 * Start addresses for the final memory configuration 126 * (Set up by the startup code) 127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 128 */ 129 #define CONFIG_SYS_SDRAM_BASE0 0x00000000 130 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 131 132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 133 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 134 135 #define CONFIG_SYS_MONITOR_LEN 0x20000 136 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 137 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 138 139 /* 140 * For booting Linux, the board info and command line data 141 * have to be in the first 8 MB of memory, since this is 142 * the maximum mapped by the Linux kernel during initialization ?? 143 */ 144 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 145 146 /*----------------------------------------------------------------------- 147 * FLASH organization 148 */ 149 #define CONFIG_FLASH_SHOW_PROGRESS 45 150 151 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 152 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 153 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 154 155 #define CONFIG_SYS_MAX_FLASH_SECT 128 156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 158 #define CONFIG_SYS_FLASH_PROTECTION 159 160 #define CONFIG_SYS_FLASH_CFI 161 #define CONFIG_FLASH_CFI_DRIVER 162 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 163 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 164 165 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 166 167 /*----------------------------------------------------------------------- 168 * Cache Configuration 169 */ 170 #define CONFIG_SYS_CACHELINE_SIZE 16 171 172 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 173 CONFIG_SYS_INIT_RAM_SIZE - 8) 174 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 175 CONFIG_SYS_INIT_RAM_SIZE - 4) 176 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 177 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 178 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 179 CF_ACR_EN | CF_ACR_SM_ALL) 180 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 181 CF_CACR_CEIB | CF_CACR_DBWE | \ 182 CF_CACR_EUSP) 183 184 /*----------------------------------------------------------------------- 185 * Memory bank definitions 186 */ 187 188 #define CONFIG_SYS_CS0_BASE 0xFF000000 189 #define CONFIG_SYS_CS0_CTRL 0x00001980 190 #define CONFIG_SYS_CS0_MASK 0x00FF0001 191 192 #define CONFIG_SYS_CS2_BASE 0xE0000000 193 #define CONFIG_SYS_CS2_CTRL 0x00001980 194 #define CONFIG_SYS_CS2_MASK 0x000F0001 195 196 #define CONFIG_SYS_CS3_BASE 0xE0100000 197 #define CONFIG_SYS_CS3_CTRL 0x00001980 198 #define CONFIG_SYS_CS3_MASK 0x000F0001 199 200 /*----------------------------------------------------------------------- 201 * Port configuration 202 */ 203 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 204 #define CONFIG_SYS_PADDR 0x0000000 205 #define CONFIG_SYS_PADAT 0x0000000 206 207 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 208 #define CONFIG_SYS_PBDDR 0x0000000 209 #define CONFIG_SYS_PBDAT 0x0000000 210 211 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 212 #define CONFIG_SYS_PCDDR 0x0000000 213 #define CONFIG_SYS_PCDAT 0x0000000 214 215 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 216 #define CONFIG_SYS_PCDDR 0x0000000 217 #define CONFIG_SYS_PCDAT 0x0000000 218 219 #define CONFIG_SYS_PASPAR 0x0F0F 220 #define CONFIG_SYS_PEHLPAR 0xC0 221 #define CONFIG_SYS_PUAPAR 0x0F 222 #define CONFIG_SYS_DDRUA 0x05 223 #define CONFIG_SYS_PJPAR 0xFF 224 225 /*----------------------------------------------------------------------- 226 * I2C 227 */ 228 229 #define CONFIG_SYS_I2C 230 #define CONFIG_SYS_I2C_FSL 231 232 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 233 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 234 235 #define CONFIG_SYS_FSL_I2C_SPEED 100000 236 #define CONFIG_SYS_FSL_I2C_SLAVE 0 237 238 #ifdef CONFIG_CMD_DATE 239 #define CONFIG_RTC_DS1338 240 #define CONFIG_I2C_RTC_ADDR 0x68 241 #endif 242 243 /*----------------------------------------------------------------------- 244 * VIDEO configuration 245 */ 246 247 #ifdef CONFIG_VIDEO 248 #define CONFIG_VIDEO_VCXK 1 249 250 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 251 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 252 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 253 254 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 255 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 256 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 257 258 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 259 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 260 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 261 262 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 263 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 264 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 265 266 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 267 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 268 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 269 270 #endif /* CONFIG_VIDEO */ 271 #endif /* _CONFIG_M5282EVB_H */ 272 /*---------------------------------------------------------------------*/ 273