1*eb0b43f2SJens Scharsig /* 2*eb0b43f2SJens Scharsig * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 3*eb0b43f2SJens Scharsig * 4*eb0b43f2SJens Scharsig * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 5*eb0b43f2SJens Scharsig * 6*eb0b43f2SJens Scharsig * See file CREDITS for list of people who contributed to this 7*eb0b43f2SJens Scharsig * project. 8*eb0b43f2SJens Scharsig * 9*eb0b43f2SJens Scharsig * This program is free software; you can redistribute it and/or 10*eb0b43f2SJens Scharsig * modify it under the terms of the GNU General Public License as 11*eb0b43f2SJens Scharsig * published by the Free Software Foundation; either version 2 of 12*eb0b43f2SJens Scharsig * the License, or (at your option) any later version. 13*eb0b43f2SJens Scharsig * 14*eb0b43f2SJens Scharsig * This program is distributed in the hope that it will be useful, 15*eb0b43f2SJens Scharsig * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*eb0b43f2SJens Scharsig * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*eb0b43f2SJens Scharsig * GNU General Public License for more details. 18*eb0b43f2SJens Scharsig * 19*eb0b43f2SJens Scharsig * You should have received a copy of the GNU General Public License 20*eb0b43f2SJens Scharsig * along with this program; if not, write to the Free Software 21*eb0b43f2SJens Scharsig * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*eb0b43f2SJens Scharsig * MA 02111-1307 USA 23*eb0b43f2SJens Scharsig */ 24*eb0b43f2SJens Scharsig 25*eb0b43f2SJens Scharsig #ifndef _CONFIG_EB_CPU5282_H_ 26*eb0b43f2SJens Scharsig #define _CONFIG_EB_CPU5282_H_ 27*eb0b43f2SJens Scharsig 28*eb0b43f2SJens Scharsig #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 29*eb0b43f2SJens Scharsig 30*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 31*eb0b43f2SJens Scharsig * High Level Configuration Options (easy to change) * 32*eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 33*eb0b43f2SJens Scharsig 34*eb0b43f2SJens Scharsig #define CONFIG_MCF52x2 /* define processor family */ 35*eb0b43f2SJens Scharsig #define CONFIG_M5282 /* define processor type */ 36*eb0b43f2SJens Scharsig 37*eb0b43f2SJens Scharsig #define CONFIG_MISC_INIT_R 38*eb0b43f2SJens Scharsig 39*eb0b43f2SJens Scharsig #define CONFIG_MCFUART 40*eb0b43f2SJens Scharsig #define CONFIG_SYS_UART_PORT (0) 41*eb0b43f2SJens Scharsig #define CONFIG_BAUDRATE 9600 42*eb0b43f2SJens Scharsig 43*eb0b43f2SJens Scharsig #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 44*eb0b43f2SJens Scharsig 45*eb0b43f2SJens Scharsig #define CONFIG_BOOTCOMMAND "printenv" 46*eb0b43f2SJens Scharsig 47*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 48*eb0b43f2SJens Scharsig * Options * 49*eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 50*eb0b43f2SJens Scharsig 51*eb0b43f2SJens Scharsig #define CONFIG_BOOT_RETRY_TIME -1 52*eb0b43f2SJens Scharsig #define CONFIG_RESET_TO_RETRY 53*eb0b43f2SJens Scharsig #define CONFIG_SPLASH_SCREEN 54*eb0b43f2SJens Scharsig 55*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 56*eb0b43f2SJens Scharsig * Configuration for environment * 57*eb0b43f2SJens Scharsig * Environment is in the second sector of the first 256k of flash * 58*eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 59*eb0b43f2SJens Scharsig 60*eb0b43f2SJens Scharsig #ifndef CONFIG_MONITOR_IS_IN_RAM 61*eb0b43f2SJens Scharsig #define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */ 62*eb0b43f2SJens Scharsig #define CONFIG_ENV_SECT_SIZE 0x4000 63*eb0b43f2SJens Scharsig #define CONFIG_ENV_IS_IN_FLASH 1 64*eb0b43f2SJens Scharsig #else 65*eb0b43f2SJens Scharsig #define CONFIG_ENV_ADDR 0xFFE04000 66*eb0b43f2SJens Scharsig #define CONFIG_ENV_SECT_SIZE 0x2000 67*eb0b43f2SJens Scharsig #define CONFIG_ENV_IS_IN_FLASH 1 68*eb0b43f2SJens Scharsig #endif 69*eb0b43f2SJens Scharsig 70*eb0b43f2SJens Scharsig /* 71*eb0b43f2SJens Scharsig * BOOTP options 72*eb0b43f2SJens Scharsig */ 73*eb0b43f2SJens Scharsig #define CONFIG_BOOTP_BOOTFILESIZE 74*eb0b43f2SJens Scharsig #define CONFIG_BOOTP_BOOTPATH 75*eb0b43f2SJens Scharsig #define CONFIG_BOOTP_GATEWAY 76*eb0b43f2SJens Scharsig #define CONFIG_BOOTP_HOSTNAME 77*eb0b43f2SJens Scharsig 78*eb0b43f2SJens Scharsig /* 79*eb0b43f2SJens Scharsig * Command line configuration. 80*eb0b43f2SJens Scharsig */ 81*eb0b43f2SJens Scharsig #include <config_cmd_default.h> 82*eb0b43f2SJens Scharsig 83*eb0b43f2SJens Scharsig #undef CONFIG_CMD_LOADB 84*eb0b43f2SJens Scharsig #define CONFIG_CMD_MII 85*eb0b43f2SJens Scharsig #define CONFIG_CMD_NET 86*eb0b43f2SJens Scharsig 87*eb0b43f2SJens Scharsig #define CONFIG_MCFTMR 88*eb0b43f2SJens Scharsig 89*eb0b43f2SJens Scharsig 90*eb0b43f2SJens Scharsig #define CONFIG_BOOTDELAY 5 91*eb0b43f2SJens Scharsig #define CONFIG_SYS_HUSH_PARSER 92*eb0b43f2SJens Scharsig #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 93*eb0b43f2SJens Scharsig #define CONFIG_SYS_PROMPT "\nEB+CPU5282> " 94*eb0b43f2SJens Scharsig #define CONFIG_SYS_LONGHELP 1 95*eb0b43f2SJens Scharsig 96*eb0b43f2SJens Scharsig #if defined(CONFIG_CMD_KGDB) 97*eb0b43f2SJens Scharsig #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 98*eb0b43f2SJens Scharsig #else 99*eb0b43f2SJens Scharsig #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 100*eb0b43f2SJens Scharsig #endif 101*eb0b43f2SJens Scharsig #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 102*eb0b43f2SJens Scharsig #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 103*eb0b43f2SJens Scharsig #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 104*eb0b43f2SJens Scharsig 105*eb0b43f2SJens Scharsig #define CONFIG_SYS_LOAD_ADDR 0x20000 106*eb0b43f2SJens Scharsig 107*eb0b43f2SJens Scharsig #define CONFIG_SYS_MEMTEST_START 0x100000 108*eb0b43f2SJens Scharsig #define CONFIG_SYS_MEMTEST_END 0x400000 109*eb0b43f2SJens Scharsig /*#define CONFIG_SYS_DRAM_TEST 1 */ 110*eb0b43f2SJens Scharsig #undef CONFIG_SYS_DRAM_TEST 111*eb0b43f2SJens Scharsig 112*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 113*eb0b43f2SJens Scharsig * Clock and PLL Configuration * 114*eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 115*eb0b43f2SJens Scharsig #define CONFIG_SYS_HZ 10000000 116*eb0b43f2SJens Scharsig #define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */ 117*eb0b43f2SJens Scharsig 118*eb0b43f2SJens Scharsig /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 119*eb0b43f2SJens Scharsig 120*eb0b43f2SJens Scharsig #define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */ 121*eb0b43f2SJens Scharsig #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 122*eb0b43f2SJens Scharsig 123*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 124*eb0b43f2SJens Scharsig * Network * 125*eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 126*eb0b43f2SJens Scharsig 127*eb0b43f2SJens Scharsig #define CONFIG_MCFFEC 128*eb0b43f2SJens Scharsig #define CONFIG_MII 1 129*eb0b43f2SJens Scharsig #define CONFIG_MII_INIT 1 130*eb0b43f2SJens Scharsig #define CONFIG_SYS_DISCOVER_PHY 131*eb0b43f2SJens Scharsig #define CONFIG_SYS_RX_ETH_BUFFER 8 132*eb0b43f2SJens Scharsig #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 133*eb0b43f2SJens Scharsig 134*eb0b43f2SJens Scharsig #define CONFIG_SYS_FEC0_PINMUX 0 135*eb0b43f2SJens Scharsig #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 136*eb0b43f2SJens Scharsig #define MCFFEC_TOUT_LOOP 50000 137*eb0b43f2SJens Scharsig 138*eb0b43f2SJens Scharsig #define CONFIG_ETHADDR 00:CF:52:82:EB:01 139*eb0b43f2SJens Scharsig #define CONFIG_OVERWRITE_ETHADDR_ONCE 140*eb0b43f2SJens Scharsig 141*eb0b43f2SJens Scharsig /*------------------------------------------------------------------------- 142*eb0b43f2SJens Scharsig * Low Level Configuration Settings 143*eb0b43f2SJens Scharsig * (address mappings, register initial values, etc.) 144*eb0b43f2SJens Scharsig * You should know what you are doing if you make changes here. 145*eb0b43f2SJens Scharsig *-----------------------------------------------------------------------*/ 146*eb0b43f2SJens Scharsig 147*eb0b43f2SJens Scharsig #define CONFIG_SYS_MBAR 0x40000000 148*eb0b43f2SJens Scharsig 149*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 150*eb0b43f2SJens Scharsig * Definitions for initial stack pointer and data area (in DPRAM) 151*eb0b43f2SJens Scharsig *-----------------------------------------------------------------------*/ 152*eb0b43f2SJens Scharsig 153*eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 154*eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 155*eb0b43f2SJens Scharsig #define CONFIG_SYS_GBL_DATA_OFFSET \ 156*eb0b43f2SJens Scharsig (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 157*eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 158*eb0b43f2SJens Scharsig 159*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 160*eb0b43f2SJens Scharsig * Start addresses for the final memory configuration 161*eb0b43f2SJens Scharsig * (Set up by the startup code) 162*eb0b43f2SJens Scharsig * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 163*eb0b43f2SJens Scharsig */ 164*eb0b43f2SJens Scharsig #define CONFIG_SYS_SDRAM_BASE1 0x00000000 165*eb0b43f2SJens Scharsig #define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */ 166*eb0b43f2SJens Scharsig 167*eb0b43f2SJens Scharsig #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1 168*eb0b43f2SJens Scharsig #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1 169*eb0b43f2SJens Scharsig 170*eb0b43f2SJens Scharsig 171*eb0b43f2SJens Scharsig /* If M5282 port is fully implemented the monitor base will be behind 172*eb0b43f2SJens Scharsig * the vector table. */ 173*eb0b43f2SJens Scharsig #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 174*eb0b43f2SJens Scharsig #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 175*eb0b43f2SJens Scharsig #else 176*eb0b43f2SJens Scharsig #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 177*eb0b43f2SJens Scharsig #endif 178*eb0b43f2SJens Scharsig 179*eb0b43f2SJens Scharsig #define CONFIG_SYS_MONITOR_LEN 0x20000 180*eb0b43f2SJens Scharsig #define CONFIG_SYS_MALLOC_LEN (256 << 10) 181*eb0b43f2SJens Scharsig #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 182*eb0b43f2SJens Scharsig 183*eb0b43f2SJens Scharsig /* 184*eb0b43f2SJens Scharsig * For booting Linux, the board info and command line data 185*eb0b43f2SJens Scharsig * have to be in the first 8 MB of memory, since this is 186*eb0b43f2SJens Scharsig * the maximum mapped by the Linux kernel during initialization ?? 187*eb0b43f2SJens Scharsig */ 188*eb0b43f2SJens Scharsig #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 189*eb0b43f2SJens Scharsig 190*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 191*eb0b43f2SJens Scharsig * FLASH organization 192*eb0b43f2SJens Scharsig */ 193*eb0b43f2SJens Scharsig 194*eb0b43f2SJens Scharsig #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 195*eb0b43f2SJens Scharsig #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 196*eb0b43f2SJens Scharsig #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 197*eb0b43f2SJens Scharsig 198*eb0b43f2SJens Scharsig #define CONFIG_SYS_MAX_FLASH_SECT 35 199*eb0b43f2SJens Scharsig #define CONFIG_SYS_MAX_FLASH_BANKS 2 200*eb0b43f2SJens Scharsig #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 201*eb0b43f2SJens Scharsig #define CONFIG_SYS_FLASH_PROTECTION 202*eb0b43f2SJens Scharsig 203*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 204*eb0b43f2SJens Scharsig * Cache Configuration 205*eb0b43f2SJens Scharsig */ 206*eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHELINE_SIZE 16 207*eb0b43f2SJens Scharsig 208*eb0b43f2SJens Scharsig #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209*eb0b43f2SJens Scharsig CONFIG_SYS_INIT_RAM_SIZE - 8) 210*eb0b43f2SJens Scharsig #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 211*eb0b43f2SJens Scharsig CONFIG_SYS_INIT_RAM_SIZE - 4) 212*eb0b43f2SJens Scharsig #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 213*eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 214*eb0b43f2SJens Scharsig CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 215*eb0b43f2SJens Scharsig CF_ACR_EN | CF_ACR_SM_ALL) 216*eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 217*eb0b43f2SJens Scharsig CF_CACR_CEIB | CF_CACR_DBWE | \ 218*eb0b43f2SJens Scharsig CF_CACR_EUSP) 219*eb0b43f2SJens Scharsig 220*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 221*eb0b43f2SJens Scharsig * Memory bank definitions 222*eb0b43f2SJens Scharsig */ 223*eb0b43f2SJens Scharsig 224*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS0_BASE 0xFFE00000 225*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS0_CTRL 0x00001980 226*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS0_MASK 0x001F0001 227*eb0b43f2SJens Scharsig 228*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS3_BASE 0xE0000000 229*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS0_CTRL 0x00001980 230*eb0b43f2SJens Scharsig #define CONFIG_SYS_CS3_MASK 0x000F0001 231*eb0b43f2SJens Scharsig 232*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 233*eb0b43f2SJens Scharsig * Port configuration 234*eb0b43f2SJens Scharsig */ 235*eb0b43f2SJens Scharsig #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 236*eb0b43f2SJens Scharsig #define CONFIG_SYS_PADDR 0x0000000 237*eb0b43f2SJens Scharsig #define CONFIG_SYS_PADAT 0x0000000 238*eb0b43f2SJens Scharsig 239*eb0b43f2SJens Scharsig #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 240*eb0b43f2SJens Scharsig #define CONFIG_SYS_PBDDR 0x0000000 241*eb0b43f2SJens Scharsig #define CONFIG_SYS_PBDAT 0x0000000 242*eb0b43f2SJens Scharsig 243*eb0b43f2SJens Scharsig #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 244*eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDDR 0x0000000 245*eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDAT 0x0000000 246*eb0b43f2SJens Scharsig 247*eb0b43f2SJens Scharsig #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 248*eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDDR 0x0000000 249*eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDAT 0x0000000 250*eb0b43f2SJens Scharsig 251*eb0b43f2SJens Scharsig #define CONFIG_SYS_PEHLPAR 0xC0 252*eb0b43f2SJens Scharsig #define CONFIG_SYS_PUAPAR 0x0F 253*eb0b43f2SJens Scharsig #define CONFIG_SYS_DDRUA 0x05 254*eb0b43f2SJens Scharsig #define CONFIG_SYS_PJPAR 0xFF 255*eb0b43f2SJens Scharsig 256*eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 257*eb0b43f2SJens Scharsig * VIDEO configuration 258*eb0b43f2SJens Scharsig */ 259*eb0b43f2SJens Scharsig 260*eb0b43f2SJens Scharsig #define CONFIG_VIDEO 261*eb0b43f2SJens Scharsig 262*eb0b43f2SJens Scharsig #ifdef CONFIG_VIDEO 263*eb0b43f2SJens Scharsig #define CONFIG_VIDEO_VCXK 1 264*eb0b43f2SJens Scharsig 265*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 266*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 267*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE 268*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_AUTODETECT 1 269*eb0b43f2SJens Scharsig 270*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 271*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 272*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 273*eb0b43f2SJens Scharsig 274*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 275*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 276*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 277*eb0b43f2SJens Scharsig 278*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 279*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 280*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 281*eb0b43f2SJens Scharsig 282*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 283*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 284*eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 285*eb0b43f2SJens Scharsig 286*eb0b43f2SJens Scharsig #endif /* CONFIG_VIDEO */ 287*eb0b43f2SJens Scharsig #endif /* _CONFIG_M5282EVB_H */ 288*eb0b43f2SJens Scharsig /*---------------------------------------------------------------------*/ 289