1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2eb0b43f2SJens Scharsig /* 3eb0b43f2SJens Scharsig * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 4eb0b43f2SJens Scharsig * 5eb0b43f2SJens Scharsig * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 6eb0b43f2SJens Scharsig */ 7eb0b43f2SJens Scharsig 8eb0b43f2SJens Scharsig #ifndef _CONFIG_EB_CPU5282_H_ 9eb0b43f2SJens Scharsig #define _CONFIG_EB_CPU5282_H_ 10eb0b43f2SJens Scharsig 11eb0b43f2SJens Scharsig #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 12eb0b43f2SJens Scharsig 13eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 14eb0b43f2SJens Scharsig * High Level Configuration Options (easy to change) * 15eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 16eb0b43f2SJens Scharsig 17eb0b43f2SJens Scharsig #define CONFIG_MCFUART 18eb0b43f2SJens Scharsig #define CONFIG_SYS_UART_PORT (0) 19eb0b43f2SJens Scharsig 20eb0b43f2SJens Scharsig #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 21eb0b43f2SJens Scharsig 22eb0b43f2SJens Scharsig #define CONFIG_BOOTCOMMAND "printenv" 23eb0b43f2SJens Scharsig 24eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 25eb0b43f2SJens Scharsig * Options * 26eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 27eb0b43f2SJens Scharsig 28eb0b43f2SJens Scharsig #define CONFIG_BOOT_RETRY_TIME -1 29eb0b43f2SJens Scharsig #define CONFIG_RESET_TO_RETRY 30eb0b43f2SJens Scharsig #define CONFIG_SPLASH_SCREEN 31eb0b43f2SJens Scharsig 32d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_HW_WATCHDOG 33d858c335SJens Scharsig (BuS Elektronik) 34d858c335SJens Scharsig (BuS Elektronik) #define STATUS_LED_ACTIVE 0 35d858c335SJens Scharsig (BuS Elektronik) 36eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 37eb0b43f2SJens Scharsig * Configuration for environment * 38eb0b43f2SJens Scharsig * Environment is in the second sector of the first 256k of flash * 39eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 40eb0b43f2SJens Scharsig 41d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_ENV_ADDR 0xFF040000 42d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_ENV_SECT_SIZE 0x00020000 43eb0b43f2SJens Scharsig 44eb0b43f2SJens Scharsig /* 45eb0b43f2SJens Scharsig * BOOTP options 46eb0b43f2SJens Scharsig */ 47eb0b43f2SJens Scharsig #define CONFIG_BOOTP_BOOTFILESIZE 48eb0b43f2SJens Scharsig 49eb0b43f2SJens Scharsig /* 50eb0b43f2SJens Scharsig * Command line configuration. 51eb0b43f2SJens Scharsig */ 52eb0b43f2SJens Scharsig 53eb0b43f2SJens Scharsig #define CONFIG_MCFTMR 54eb0b43f2SJens Scharsig 55eb0b43f2SJens Scharsig #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 56eb0b43f2SJens Scharsig #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 57eb0b43f2SJens Scharsig 58eb0b43f2SJens Scharsig #define CONFIG_SYS_LOAD_ADDR 0x20000 59eb0b43f2SJens Scharsig 60eb0b43f2SJens Scharsig #define CONFIG_SYS_MEMTEST_START 0x100000 61eb0b43f2SJens Scharsig #define CONFIG_SYS_MEMTEST_END 0x400000 62eb0b43f2SJens Scharsig /*#define CONFIG_SYS_DRAM_TEST 1 */ 63eb0b43f2SJens Scharsig #undef CONFIG_SYS_DRAM_TEST 64eb0b43f2SJens Scharsig 65eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 66eb0b43f2SJens Scharsig * Clock and PLL Configuration * 67eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 68d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 69eb0b43f2SJens Scharsig 70d858c335SJens Scharsig (BuS Elektronik) /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 71eb0b43f2SJens Scharsig 72d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 73eb0b43f2SJens Scharsig #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 74eb0b43f2SJens Scharsig 75eb0b43f2SJens Scharsig /*----------------------------------------------------------------------* 76eb0b43f2SJens Scharsig * Network * 77eb0b43f2SJens Scharsig *----------------------------------------------------------------------*/ 78eb0b43f2SJens Scharsig 79eb0b43f2SJens Scharsig #define CONFIG_MCFFEC 80eb0b43f2SJens Scharsig #define CONFIG_MII_INIT 1 81eb0b43f2SJens Scharsig #define CONFIG_SYS_DISCOVER_PHY 82eb0b43f2SJens Scharsig #define CONFIG_SYS_RX_ETH_BUFFER 8 83eb0b43f2SJens Scharsig #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 84eb0b43f2SJens Scharsig 85eb0b43f2SJens Scharsig #define CONFIG_SYS_FEC0_PINMUX 0 86eb0b43f2SJens Scharsig #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 87eb0b43f2SJens Scharsig #define MCFFEC_TOUT_LOOP 50000 88eb0b43f2SJens Scharsig 89eb0b43f2SJens Scharsig #define CONFIG_OVERWRITE_ETHADDR_ONCE 90eb0b43f2SJens Scharsig 91eb0b43f2SJens Scharsig /*------------------------------------------------------------------------- 92eb0b43f2SJens Scharsig * Low Level Configuration Settings 93eb0b43f2SJens Scharsig * (address mappings, register initial values, etc.) 94eb0b43f2SJens Scharsig * You should know what you are doing if you make changes here. 95eb0b43f2SJens Scharsig *-----------------------------------------------------------------------*/ 96eb0b43f2SJens Scharsig 97eb0b43f2SJens Scharsig #define CONFIG_SYS_MBAR 0x40000000 98eb0b43f2SJens Scharsig 99eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 100eb0b43f2SJens Scharsig * Definitions for initial stack pointer and data area (in DPRAM) 101eb0b43f2SJens Scharsig *-----------------------------------------------------------------------*/ 102eb0b43f2SJens Scharsig 103eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 104eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 105eb0b43f2SJens Scharsig #define CONFIG_SYS_GBL_DATA_OFFSET \ 106eb0b43f2SJens Scharsig (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 107eb0b43f2SJens Scharsig #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 108eb0b43f2SJens Scharsig 109eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 110eb0b43f2SJens Scharsig * Start addresses for the final memory configuration 111eb0b43f2SJens Scharsig * (Set up by the startup code) 112eb0b43f2SJens Scharsig * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 113eb0b43f2SJens Scharsig */ 114d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_SDRAM_BASE0 0x00000000 115d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 116eb0b43f2SJens Scharsig 117d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 118d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 119eb0b43f2SJens Scharsig 120eb0b43f2SJens Scharsig #define CONFIG_SYS_MONITOR_LEN 0x20000 1218c89443eSJens Scharsig (BuS Elektronik) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 122eb0b43f2SJens Scharsig #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 123eb0b43f2SJens Scharsig 124eb0b43f2SJens Scharsig /* 125eb0b43f2SJens Scharsig * For booting Linux, the board info and command line data 126eb0b43f2SJens Scharsig * have to be in the first 8 MB of memory, since this is 127eb0b43f2SJens Scharsig * the maximum mapped by the Linux kernel during initialization ?? 128eb0b43f2SJens Scharsig */ 129eb0b43f2SJens Scharsig #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 130eb0b43f2SJens Scharsig 131eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 132eb0b43f2SJens Scharsig * FLASH organization 133eb0b43f2SJens Scharsig */ 134d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_FLASH_SHOW_PROGRESS 45 135eb0b43f2SJens Scharsig 136eb0b43f2SJens Scharsig #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 137eb0b43f2SJens Scharsig #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 138eb0b43f2SJens Scharsig #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 139eb0b43f2SJens Scharsig 140d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_MAX_FLASH_SECT 128 141d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_MAX_FLASH_BANKS 1 142eb0b43f2SJens Scharsig #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 143eb0b43f2SJens Scharsig 144d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 145d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 146d858c335SJens Scharsig (BuS Elektronik) 147d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 148d858c335SJens Scharsig (BuS Elektronik) 149eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 150eb0b43f2SJens Scharsig * Cache Configuration 151eb0b43f2SJens Scharsig */ 152eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHELINE_SIZE 16 153eb0b43f2SJens Scharsig 154eb0b43f2SJens Scharsig #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 155eb0b43f2SJens Scharsig CONFIG_SYS_INIT_RAM_SIZE - 8) 156eb0b43f2SJens Scharsig #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 157eb0b43f2SJens Scharsig CONFIG_SYS_INIT_RAM_SIZE - 4) 158eb0b43f2SJens Scharsig #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 159eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 160eb0b43f2SJens Scharsig CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 161eb0b43f2SJens Scharsig CF_ACR_EN | CF_ACR_SM_ALL) 162eb0b43f2SJens Scharsig #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 163eb0b43f2SJens Scharsig CF_CACR_CEIB | CF_CACR_DBWE | \ 164eb0b43f2SJens Scharsig CF_CACR_EUSP) 165eb0b43f2SJens Scharsig 166eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 167eb0b43f2SJens Scharsig * Memory bank definitions 168eb0b43f2SJens Scharsig */ 169eb0b43f2SJens Scharsig 170d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS0_BASE 0xFF000000 171eb0b43f2SJens Scharsig #define CONFIG_SYS_CS0_CTRL 0x00001980 172d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS0_MASK 0x00FF0001 173eb0b43f2SJens Scharsig 174d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS2_BASE 0xE0000000 175d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS2_CTRL 0x00001980 176d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS2_MASK 0x000F0001 177d858c335SJens Scharsig (BuS Elektronik) 178d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS3_BASE 0xE0100000 179d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_CS3_CTRL 0x00001980 180eb0b43f2SJens Scharsig #define CONFIG_SYS_CS3_MASK 0x000F0001 181eb0b43f2SJens Scharsig 182eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 183eb0b43f2SJens Scharsig * Port configuration 184eb0b43f2SJens Scharsig */ 185eb0b43f2SJens Scharsig #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 186eb0b43f2SJens Scharsig #define CONFIG_SYS_PADDR 0x0000000 187eb0b43f2SJens Scharsig #define CONFIG_SYS_PADAT 0x0000000 188eb0b43f2SJens Scharsig 189eb0b43f2SJens Scharsig #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 190eb0b43f2SJens Scharsig #define CONFIG_SYS_PBDDR 0x0000000 191eb0b43f2SJens Scharsig #define CONFIG_SYS_PBDAT 0x0000000 192eb0b43f2SJens Scharsig 193eb0b43f2SJens Scharsig #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 194eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDDR 0x0000000 195eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDAT 0x0000000 196eb0b43f2SJens Scharsig 197eb0b43f2SJens Scharsig #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 198eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDDR 0x0000000 199eb0b43f2SJens Scharsig #define CONFIG_SYS_PCDAT 0x0000000 200eb0b43f2SJens Scharsig 201d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_PASPAR 0x0F0F 202eb0b43f2SJens Scharsig #define CONFIG_SYS_PEHLPAR 0xC0 203eb0b43f2SJens Scharsig #define CONFIG_SYS_PUAPAR 0x0F 204eb0b43f2SJens Scharsig #define CONFIG_SYS_DDRUA 0x05 205eb0b43f2SJens Scharsig #define CONFIG_SYS_PJPAR 0xFF 206eb0b43f2SJens Scharsig 207eb0b43f2SJens Scharsig /*----------------------------------------------------------------------- 208d858c335SJens Scharsig (BuS Elektronik) * I2C 209d858c335SJens Scharsig (BuS Elektronik) */ 210d858c335SJens Scharsig (BuS Elektronik) 21100f792e0SHeiko Schocher #define CONFIG_SYS_I2C 21200f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 213d858c335SJens Scharsig (BuS Elektronik) 21400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 215d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 216d858c335SJens Scharsig (BuS Elektronik) 21700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 100000 21800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0 219d858c335SJens Scharsig (BuS Elektronik) 220d858c335SJens Scharsig (BuS Elektronik) #ifdef CONFIG_CMD_DATE 221d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_RTC_DS1338 222d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_I2C_RTC_ADDR 0x68 223d858c335SJens Scharsig (BuS Elektronik) #endif 224d858c335SJens Scharsig (BuS Elektronik) 225d858c335SJens Scharsig (BuS Elektronik) /*----------------------------------------------------------------------- 226eb0b43f2SJens Scharsig * VIDEO configuration 227eb0b43f2SJens Scharsig */ 228eb0b43f2SJens Scharsig 229eb0b43f2SJens Scharsig #ifdef CONFIG_VIDEO 230eb0b43f2SJens Scharsig #define CONFIG_VIDEO_VCXK 1 231eb0b43f2SJens Scharsig 232eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 233eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 234d858c335SJens Scharsig (BuS Elektronik) #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 235eb0b43f2SJens Scharsig 236eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 237eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 238eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 239eb0b43f2SJens Scharsig 240eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 241eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 242eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 243eb0b43f2SJens Scharsig 244eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 245eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 246eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 247eb0b43f2SJens Scharsig 248eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 249eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 250eb0b43f2SJens Scharsig #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 251eb0b43f2SJens Scharsig 252eb0b43f2SJens Scharsig #endif /* CONFIG_VIDEO */ 253eb0b43f2SJens Scharsig #endif /* _CONFIG_M5282EVB_H */ 254eb0b43f2SJens Scharsig /*---------------------------------------------------------------------*/ 255