1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_SYNOLOGY_DS414_H 8 #define _CONFIG_SYNOLOGY_DS414_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 27 /* I2C */ 28 #define CONFIG_SYS_I2C 29 #define CONFIG_SYS_I2C_MVTWSI 30 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 31 #define CONFIG_SYS_I2C_SLAVE 0x0 32 #define CONFIG_SYS_I2C_SPEED 100000 33 34 /* SPI NOR flash default params, used by sf commands */ 35 #define CONFIG_SF_DEFAULT_SPEED 1000000 36 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 37 38 /* Environment in SPI NOR flash */ 39 #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ 40 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 41 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 42 43 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 44 #define CONFIG_PHY_ADDR { 0x1, 0x0 } 45 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 46 47 #define CONFIG_SYS_ALT_MEMTEST 48 49 /* PCIe support */ 50 #ifndef CONFIG_SPL_BUILD 51 #define CONFIG_CMD_PCI 52 #define CONFIG_CMD_PCI_ENUM 53 #define CONFIG_PCI_MVEBU 54 #define CONFIG_PCI_SCAN_SHOW 55 #endif 56 57 /* USB/EHCI/XHCI configuration */ 58 59 #define CONFIG_DM_USB 60 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 61 62 /* FIXME: broken XHCI support 63 * Below defines should enable support for the two rear USB3 ports. Sadly, this 64 * does not work because: 65 * - xhci-pci seems to not support DM_USB, so with that enabled it is not 66 * found. 67 * - USB init fails, controller does not respond in time */ 68 #if 0 69 #undef CONFIG_DM_USB 70 #define CONFIG_USB_XHCI_PCI 71 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 72 #endif 73 74 #if !defined(CONFIG_USB_XHCI_HCD) 75 #define CONFIG_EHCI_IS_TDI 76 #endif 77 78 /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */ 79 #define CONFIG_SUPPORT_VFAT 80 #define CONFIG_SYS_MVFS 81 82 /* 83 * mv-common.h should be defined after CMD configs since it used them 84 * to enable certain macros 85 */ 86 #include "mv-common.h" 87 88 /* 89 * Memory layout while starting into the bin_hdr via the 90 * BootROM: 91 * 92 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 93 * 0x4000.4030 bin_hdr start address 94 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 95 * 0x4007.fffc BootROM stack top 96 * 97 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 98 * L2 cache thus cannot be used. 99 */ 100 101 /* SPL */ 102 /* Defines for SPL */ 103 #define CONFIG_SPL_FRAMEWORK 104 #define CONFIG_SPL_TEXT_BASE 0x40004030 105 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 106 107 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 108 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 109 110 #ifdef CONFIG_SPL_BUILD 111 #define CONFIG_SYS_MALLOC_SIMPLE 112 #endif 113 114 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 115 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 116 117 /* SPL related SPI defines */ 118 #define CONFIG_SPL_SPI_LOAD 119 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 120 121 /* DS414 bus width is 32bits */ 122 #define CONFIG_DDR_32BIT 123 124 /* Use random ethernet address if not configured */ 125 #define CONFIG_LIB_RAND 126 #define CONFIG_NET_RANDOM_ETHADDR 127 128 /* Default Environment */ 129 #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" 130 #define CONFIG_BOOTARGS "console=ttyS0,115200" 131 #define CONFIG_LOADADDR 0x80000 132 #undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */ 133 #define CONFIG_PREBOOT "usb start; sf probe" 134 135 #endif /* _CONFIG_SYNOLOGY_DS414_H */ 136