1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated. 4 * Lokesh Vutla <lokeshvutla@ti.com> 5 * 6 * Configuration settings for the TI DRA7XX board. 7 * See ti_omap5_common.h for omap5 common settings. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_DRA7XX_EVM_H 13 #define __CONFIG_DRA7XX_EVM_H 14 15 #include <environment/ti/dfu.h> 16 17 #ifdef CONFIG_SPL_BUILD 18 #define CONFIG_IODELAY_RECALIBRATION 19 #endif 20 21 #define CONFIG_VERY_BIG_RAM 22 #define CONFIG_NR_DRAM_BANKS 2 23 #define CONFIG_MAX_MEM_MAPPED 0x80000000 24 25 #ifndef CONFIG_QSPI_BOOT 26 /* MMC ENV related defines */ 27 #define CONFIG_ENV_IS_IN_MMC 28 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ 29 #define CONFIG_ENV_SIZE (128 << 10) 30 #define CONFIG_ENV_OFFSET 0xE0000 31 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 32 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 33 #endif 34 35 #if (CONFIG_CONS_INDEX == 1) 36 #define CONSOLEDEV "ttyO0" 37 #elif (CONFIG_CONS_INDEX == 3) 38 #define CONSOLEDEV "ttyO2" 39 #endif 40 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ 41 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ 42 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ 43 44 #define CONFIG_SYS_OMAP_ABE_SYSCK 45 46 #ifndef CONFIG_SPL_BUILD 47 /* Define the default GPT table for eMMC */ 48 #define PARTS_DEFAULT \ 49 /* Linux partitions */ \ 50 "uuid_disk=${uuid_gpt_disk};" \ 51 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ 52 /* Android partitions */ \ 53 "partitions_android=" \ 54 "uuid_disk=${uuid_gpt_disk};" \ 55 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ 56 "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ 57 "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ 58 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ 59 "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ 60 "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ 61 "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ 62 "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ 63 "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ 64 "name=system,size=768M,uuid=${uuid_gpt_system};" \ 65 "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ 66 "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ 67 "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ 68 "name=userdata,size=-,uuid=${uuid_gpt_userdata}" 69 70 #define DFUARGS \ 71 "dfu_bufsiz=0x10000\0" \ 72 DFU_ALT_INFO_MMC \ 73 DFU_ALT_INFO_EMMC \ 74 DFU_ALT_INFO_RAM \ 75 DFU_ALT_INFO_QSPI 76 #else 77 /* Discard fastboot in SPL build, to spare some space */ 78 #undef CONFIG_FASTBOOT 79 #undef CONFIG_USB_FUNCTION_FASTBOOT 80 #undef CONFIG_CMD_FASTBOOT 81 #undef CONFIG_ANDROID_BOOT_IMAGE 82 #undef CONFIG_FASTBOOT_BUF_ADDR 83 #undef CONFIG_FASTBOOT_BUF_SIZE 84 #undef CONFIG_FASTBOOT_FLASH 85 #endif 86 87 #ifdef CONFIG_SPL_BUILD 88 #undef CONFIG_CMD_BOOTD 89 #ifdef CONFIG_SPL_DFU_SUPPORT 90 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 91 #define DFUARGS \ 92 "dfu_bufsiz=0x10000\0" \ 93 DFU_ALT_INFO_RAM 94 #endif 95 #endif 96 97 #include <configs/ti_omap5_common.h> 98 99 /* Enhance our eMMC support / experience. */ 100 #define CONFIG_RANDOM_UUID 101 #define CONFIG_HSMMC2_8BIT 102 103 /* CPSW Ethernet */ 104 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ 105 #define CONFIG_BOOTP_DNS2 106 #define CONFIG_BOOTP_SEND_HOSTNAME 107 #define CONFIG_BOOTP_GATEWAY 108 #define CONFIG_BOOTP_SUBNETMASK 109 #define CONFIG_NET_RETRY_COUNT 10 110 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ 111 #define CONFIG_MII /* Required in net/eth.c */ 112 #define CONFIG_PHY_GIGE /* per-board part of CPSW */ 113 #define CONFIG_PHYLIB 114 #define CONFIG_PHY_TI 115 116 /* SPI */ 117 #undef CONFIG_OMAP3_SPI 118 #define CONFIG_TI_SPI_MMAP 119 #define CONFIG_SF_DEFAULT_SPEED 76800000 120 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 121 #define CONFIG_QSPI_QUAD_SUPPORT 122 123 /* 124 * Default to using SPI for environment, etc. 125 * 0x000000 - 0x040000 : QSPI.SPL (256KiB) 126 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) 127 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) 128 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) 129 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) 130 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) 131 * 0x9E0000 - 0x2000000 : USERLAND 132 */ 133 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 134 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 135 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 136 #if defined(CONFIG_QSPI_BOOT) 137 #define CONFIG_ENV_IS_IN_SPI_FLASH 138 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 139 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 140 #define CONFIG_ENV_SIZE (64 << 10) 141 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ 142 #define CONFIG_ENV_OFFSET 0x1C0000 143 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000 144 #endif 145 146 /* SPI SPL */ 147 #define CONFIG_TI_EDMA3 148 #define CONFIG_SPL_SPI_LOAD 149 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 150 151 #define CONFIG_SUPPORT_EMMC_BOOT 152 153 /* USB xHCI HOST */ 154 #define CONFIG_USB_XHCI_OMAP 155 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 156 157 #define CONFIG_OMAP_USB_PHY 158 #define CONFIG_OMAP_USB2PHY2_HOST 159 160 /* SATA */ 161 #define CONFIG_SCSI 162 #define CONFIG_LIBATA 163 #define CONFIG_SCSI_AHCI 164 #define CONFIG_SCSI_AHCI_PLAT 165 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 166 #define CONFIG_SYS_SCSI_MAX_LUN 1 167 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 168 CONFIG_SYS_SCSI_MAX_LUN) 169 170 /* NAND support */ 171 #ifdef CONFIG_NAND 172 /* NAND: device related configs */ 173 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 174 #define CONFIG_SYS_NAND_OOBSIZE 64 175 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 176 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 177 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 178 CONFIG_SYS_NAND_PAGE_SIZE) 179 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 180 /* NAND: driver related configs */ 181 #define CONFIG_NAND_OMAP_GPMC 182 #define CONFIG_NAND_OMAP_ELM 183 #define CONFIG_SYS_NAND_ONFI_DETECTION 184 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 185 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 186 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 187 10, 11, 12, 13, 14, 15, 16, 17, \ 188 18, 19, 20, 21, 22, 23, 24, 25, \ 189 26, 27, 28, 29, 30, 31, 32, 33, \ 190 34, 35, 36, 37, 38, 39, 40, 41, \ 191 42, 43, 44, 45, 46, 47, 48, 49, \ 192 50, 51, 52, 53, 54, 55, 56, 57, } 193 #define CONFIG_SYS_NAND_ECCSIZE 512 194 #define CONFIG_SYS_NAND_ECCBYTES 14 195 #define MTDIDS_DEFAULT "nand0=nand.0" 196 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ 197 "128k(NAND.SPL)," \ 198 "128k(NAND.SPL.backup1)," \ 199 "128k(NAND.SPL.backup2)," \ 200 "128k(NAND.SPL.backup3)," \ 201 "256k(NAND.u-boot-spl-os)," \ 202 "1m(NAND.u-boot)," \ 203 "128k(NAND.u-boot-env)," \ 204 "128k(NAND.u-boot-env.backup1)," \ 205 "8m(NAND.kernel)," \ 206 "-(NAND.file-system)" 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 208 /* NAND: SPL related configs */ 209 #ifdef CONFIG_SPL_NAND_SUPPORT 210 #define CONFIG_SPL_NAND_AM33XX_BCH 211 #endif 212 /* NAND: SPL falcon mode configs */ 213 #ifdef CONFIG_SPL_OS_BOOT 214 #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/ 215 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ 216 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 217 #endif 218 #endif /* !CONFIG_NAND */ 219 220 /* Parallel NOR Support */ 221 #if defined(CONFIG_NOR) 222 /* NOR: device related configs */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 512 224 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 225 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ 226 /* #define CONFIG_INIT_IGNORE_ERROR */ 227 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 228 #define CONFIG_SYS_FLASH_PROTECTION 229 #define CONFIG_SYS_FLASH_CFI 230 #define CONFIG_FLASH_CFI_DRIVER 231 #define CONFIG_FLASH_CFI_MTD 232 #define CONFIG_SYS_MAX_FLASH_BANKS 1 233 #define CONFIG_SYS_FLASH_BASE (0x08000000) 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 235 /* Reduce SPL size by removing unlikey targets */ 236 #ifdef CONFIG_NOR_BOOT 237 #define CONFIG_ENV_IS_IN_FLASH 238 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ 239 #define MTDIDS_DEFAULT "nor0=physmap-flash.0" 240 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ 241 "128k(NOR.SPL)," \ 242 "128k(NOR.SPL.backup1)," \ 243 "128k(NOR.SPL.backup2)," \ 244 "128k(NOR.SPL.backup3)," \ 245 "256k(NOR.u-boot-spl-os)," \ 246 "1m(NOR.u-boot)," \ 247 "128k(NOR.u-boot-env)," \ 248 "128k(NOR.u-boot-env.backup1)," \ 249 "8m(NOR.kernel)," \ 250 "-(NOR.rootfs)" 251 #define CONFIG_ENV_OFFSET 0x001c0000 252 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 253 #endif 254 #endif /* NOR support */ 255 256 #endif /* __CONFIG_DRA7XX_EVM_H */ 257