1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * Texas Instruments Incorporated. 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Configuration settings for the TI DRA7XX board. 8 * See ti_omap5_common.h for omap5 common settings. 9 */ 10 11 #ifndef __CONFIG_DRA7XX_EVM_H 12 #define __CONFIG_DRA7XX_EVM_H 13 14 #include <environment/ti/dfu.h> 15 16 #define CONFIG_IODELAY_RECALIBRATION 17 18 #define CONFIG_VERY_BIG_RAM 19 #define CONFIG_MAX_MEM_MAPPED 0x80000000 20 21 #ifndef CONFIG_QSPI_BOOT 22 /* MMC ENV related defines */ 23 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ 24 #define CONFIG_ENV_SIZE (128 << 10) 25 #define CONFIG_ENV_OFFSET 0x260000 26 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 27 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 28 #endif 29 30 #if (CONFIG_CONS_INDEX == 1) 31 #define CONSOLEDEV "ttyO0" 32 #elif (CONFIG_CONS_INDEX == 3) 33 #define CONSOLEDEV "ttyO2" 34 #endif 35 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ 36 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ 37 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ 38 39 #define CONFIG_ENV_EEPROM_IS_ON_I2C 40 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 41 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 42 43 #define CONFIG_SYS_OMAP_ABE_SYSCK 44 45 #ifndef CONFIG_SPL_BUILD 46 #define DFUARGS \ 47 "dfu_bufsiz=0x10000\0" \ 48 DFU_ALT_INFO_MMC \ 49 DFU_ALT_INFO_EMMC \ 50 DFU_ALT_INFO_RAM \ 51 DFU_ALT_INFO_QSPI 52 #endif 53 54 #ifdef CONFIG_SPL_BUILD 55 #undef CONFIG_CMD_BOOTD 56 #ifdef CONFIG_SPL_DFU 57 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 58 #define DFUARGS \ 59 "dfu_bufsiz=0x10000\0" \ 60 DFU_ALT_INFO_RAM 61 #endif 62 #endif 63 64 #include <configs/ti_omap5_common.h> 65 66 /* Enhance our eMMC support / experience. */ 67 #define CONFIG_HSMMC2_8BIT 68 69 /* CPSW Ethernet */ 70 #define CONFIG_BOOTP_DNS2 71 #define CONFIG_BOOTP_SEND_HOSTNAME 72 #define CONFIG_NET_RETRY_COUNT 10 73 #define CONFIG_PHY_TI 74 75 /* SPI */ 76 #define CONFIG_TI_SPI_MMAP 77 #define CONFIG_SF_DEFAULT_SPEED 76800000 78 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 79 #define CONFIG_QSPI_QUAD_SUPPORT 80 81 /* 82 * Default to using SPI for environment, etc. 83 * 0x000000 - 0x040000 : QSPI.SPL (256KiB) 84 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) 85 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) 86 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) 87 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) 88 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) 89 * 0x9E0000 - 0x2000000 : USERLAND 90 */ 91 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 92 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 93 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 94 #if defined(CONFIG_QSPI_BOOT) 95 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 96 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 97 #define CONFIG_ENV_SIZE (64 << 10) 98 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ 99 #define CONFIG_ENV_OFFSET 0x1C0000 100 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000 101 #endif 102 103 /* SPI SPL */ 104 #define CONFIG_TI_EDMA3 105 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 106 107 #define CONFIG_SUPPORT_EMMC_BOOT 108 109 /* USB xHCI HOST */ 110 #define CONFIG_USB_XHCI_OMAP 111 112 #define CONFIG_OMAP_USB2PHY2_HOST 113 114 /* SATA */ 115 #define CONFIG_SCSI_AHCI_PLAT 116 117 /* NAND support */ 118 #ifdef CONFIG_NAND 119 /* NAND: device related configs */ 120 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 121 #define CONFIG_SYS_NAND_OOBSIZE 64 122 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 123 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 124 CONFIG_SYS_NAND_PAGE_SIZE) 125 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 126 /* NAND: driver related configs */ 127 #define CONFIG_SYS_NAND_ONFI_DETECTION 128 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 129 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 130 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 131 10, 11, 12, 13, 14, 15, 16, 17, \ 132 18, 19, 20, 21, 22, 23, 24, 25, \ 133 26, 27, 28, 29, 30, 31, 32, 33, \ 134 34, 35, 36, 37, 38, 39, 40, 41, \ 135 42, 43, 44, 45, 46, 47, 48, 49, \ 136 50, 51, 52, 53, 54, 55, 56, 57, } 137 #define CONFIG_SYS_NAND_ECCSIZE 512 138 #define CONFIG_SYS_NAND_ECCBYTES 14 139 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 140 /* NAND: SPL related configs */ 141 /* NAND: SPL falcon mode configs */ 142 #ifdef CONFIG_SPL_OS_BOOT 143 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ 144 #endif 145 #endif /* !CONFIG_NAND */ 146 147 /* Parallel NOR Support */ 148 #if defined(CONFIG_NOR) 149 /* NOR: device related configs */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 512 151 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 152 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ 153 /* #define CONFIG_INIT_IGNORE_ERROR */ 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 155 #define CONFIG_SYS_FLASH_BASE (0x08000000) 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 157 /* Reduce SPL size by removing unlikey targets */ 158 #ifdef CONFIG_NOR_BOOT 159 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ 160 #define CONFIG_ENV_OFFSET 0x001c0000 161 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 162 #endif 163 #endif /* NOR support */ 164 165 #endif /* __CONFIG_DRA7XX_EVM_H */ 166