1 /* 2 * DHCOM DH-iMX6 PDK board configuration 3 * 4 * Copyright (C) 2017 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __DH_IMX6_CONFIG_H 10 #define __DH_IMX6_CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 #include "mx6_common.h" 15 16 /* 17 * SPI NOR layout: 18 * 0x00_0000-0x00_ffff ... U-Boot SPL 19 * 0x01_0000-0x0f_ffff ... U-Boot 20 * 0x10_0000-0x10_ffff ... U-Boot env #1 21 * 0x11_0000-0x11_ffff ... U-Boot env #2 22 * 0x12_0000-0x1f_ffff ... UNUSED 23 */ 24 25 /* SPL */ 26 #include "imx6_spl.h" /* common IMX6 SPL configuration */ 27 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" 29 30 /* Miscellaneous configurable options */ 31 32 #define CONFIG_CMDLINE_TAG 33 #define CONFIG_SETUP_MEMORY_TAGS 34 #define CONFIG_INITRD_TAG 35 #define CONFIG_REVISION_TAG 36 37 #define CONFIG_BOUNCE_BUFFER 38 #define CONFIG_BZIP2 39 40 /* Size of malloc() pool */ 41 #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) 42 43 /* Bootcounter */ 44 #define CONFIG_SYS_BOOTCOUNT_BE 45 46 /* FEC ethernet */ 47 #define CONFIG_MII 48 #define IMX_FEC_BASE ENET_BASE_ADDR 49 #define CONFIG_FEC_XCV_TYPE RMII 50 #define CONFIG_ETHPRIME "FEC" 51 #define CONFIG_FEC_MXC_PHYADDR 0 52 #define CONFIG_ARP_TIMEOUT 200UL 53 54 /* Fuses */ 55 #ifdef CONFIG_CMD_FUSE 56 #define CONFIG_MXC_OCOTP 57 #endif 58 59 /* I2C Configs */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_I2C_MXC 62 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 63 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 64 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 65 #define CONFIG_SYS_I2C_SPEED 100000 66 67 /* MMC Configs */ 68 #define CONFIG_FSL_USDHC 69 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 70 #define CONFIG_SYS_FSL_USDHC_NUM 3 71 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ 72 73 /* SATA Configs */ 74 #ifdef CONFIG_CMD_SATA 75 #define CONFIG_SYS_SATA_MAX_DEVICE 1 76 #define CONFIG_DWC_AHSATA_PORT_ID 0 77 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 78 #define CONFIG_LBA48 79 #endif 80 81 /* SPI Flash Configs */ 82 #ifdef CONFIG_CMD_SF 83 #define CONFIG_SF_DEFAULT_BUS 0 84 #define CONFIG_SF_DEFAULT_CS 0 85 #define CONFIG_SF_DEFAULT_SPEED 25000000 86 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 87 #endif 88 89 /* UART */ 90 #define CONFIG_MXC_UART 91 #define CONFIG_MXC_UART_BASE UART1_BASE 92 #define CONFIG_BAUDRATE 115200 93 94 /* USB Configs */ 95 #ifdef CONFIG_CMD_USB 96 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 97 #define CONFIG_USB_HOST_ETHER 98 #define CONFIG_USB_ETHER_ASIX 99 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 100 #define CONFIG_MXC_USB_FLAGS 0 101 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 102 103 /* USB Gadget (DFU, UMS) */ 104 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 105 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 106 #define DFU_DEFAULT_POLL_TIMEOUT 300 107 108 /* USB IDs */ 109 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 110 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 111 #endif 112 #endif 113 114 /* Watchdog */ 115 #define CONFIG_HW_WATCHDOG 116 #define CONFIG_IMX_WATCHDOG 117 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 118 119 /* allow to overwrite serial and ethaddr */ 120 #define CONFIG_ENV_OVERWRITE 121 122 #define CONFIG_LOADADDR 0x12000000 123 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 124 125 #ifndef CONFIG_SPL_BUILD 126 #define CONFIG_EXTRA_ENV_SETTINGS \ 127 "console=ttymxc0,115200\0" \ 128 "fdt_addr=0x18000000\0" \ 129 "fdt_high=0xffffffff\0" \ 130 "initrd_high=0xffffffff\0" \ 131 "kernel_addr_r=0x10008000\0" \ 132 "fdt_addr_r=0x13000000\0" \ 133 "ramdisk_addr_r=0x18000000\0" \ 134 "scriptaddr=0x14000000\0" \ 135 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ 136 BOOTENV 137 138 #define CONFIG_BOOTCOMMAND "run distro_bootcmd" 139 140 #define BOOT_TARGET_DEVICES(func) \ 141 func(MMC, mmc, 0) \ 142 func(MMC, mmc, 2) \ 143 func(USB, usb, 1) \ 144 func(SATA, sata, 0) \ 145 func(DHCP, dhcp, na) 146 147 #include <config_distro_bootcmd.h> 148 #endif 149 150 /* Physical Memory Map */ 151 #define CONFIG_NR_DRAM_BANKS 1 152 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 153 154 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 155 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 156 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 157 158 #define CONFIG_SYS_INIT_SP_OFFSET \ 159 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 160 161 #define CONFIG_SYS_INIT_SP_ADDR \ 162 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 163 164 #define CONFIG_SYS_MEMTEST_START 0x10000000 165 #define CONFIG_SYS_MEMTEST_END 0x20000000 166 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 167 168 /* Environment */ 169 #define CONFIG_ENV_SIZE (16 * 1024) 170 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 171 172 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 173 #define CONFIG_ENV_OFFSET (1024 * 1024) 174 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 175 #define CONFIG_ENV_OFFSET_REDUND \ 176 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 177 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 178 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 179 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 180 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 181 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 182 #endif 183 184 #endif /* __DH_IMX6_CONFIG_H */ 185