1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * DHCOM DH-iMX6 PDK board configuration 4 * 5 * Copyright (C) 2017 Marek Vasut <marex@denx.de> 6 */ 7 8 #ifndef __DH_IMX6_CONFIG_H 9 #define __DH_IMX6_CONFIG_H 10 11 #include <asm/arch/imx-regs.h> 12 13 #include "mx6_common.h" 14 15 /* 16 * SPI NOR layout: 17 * 0x00_0000-0x00_ffff ... U-Boot SPL 18 * 0x01_0000-0x0f_ffff ... U-Boot 19 * 0x10_0000-0x10_ffff ... U-Boot env #1 20 * 0x11_0000-0x11_ffff ... U-Boot env #2 21 * 0x12_0000-0x1f_ffff ... UNUSED 22 */ 23 24 /* SPL */ 25 #include "imx6_spl.h" /* common IMX6 SPL configuration */ 26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" 28 29 /* Miscellaneous configurable options */ 30 31 #define CONFIG_CMDLINE_TAG 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 #define CONFIG_BZIP2 37 38 /* Size of malloc() pool */ 39 #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) 40 41 /* Bootcounter */ 42 #define CONFIG_SYS_BOOTCOUNT_BE 43 44 /* FEC ethernet */ 45 #define CONFIG_MII 46 #define IMX_FEC_BASE ENET_BASE_ADDR 47 #define CONFIG_FEC_XCV_TYPE RMII 48 #define CONFIG_ETHPRIME "FEC" 49 #define CONFIG_FEC_MXC_PHYADDR 0 50 #define CONFIG_ARP_TIMEOUT 200UL 51 52 /* Fuses */ 53 #ifdef CONFIG_CMD_FUSE 54 #define CONFIG_MXC_OCOTP 55 #endif 56 57 /* I2C Configs */ 58 #define CONFIG_SYS_I2C 59 #define CONFIG_SYS_I2C_MXC 60 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 61 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 62 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 63 #define CONFIG_SYS_I2C_SPEED 100000 64 65 /* MMC Configs */ 66 #define CONFIG_FSL_USDHC 67 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 68 #define CONFIG_SYS_FSL_USDHC_NUM 3 69 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ 70 71 /* SATA Configs */ 72 #ifdef CONFIG_CMD_SATA 73 #define CONFIG_SYS_SATA_MAX_DEVICE 1 74 #define CONFIG_DWC_AHSATA_PORT_ID 0 75 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 76 #define CONFIG_LBA48 77 #endif 78 79 /* SPI Flash Configs */ 80 #ifdef CONFIG_CMD_SF 81 #define CONFIG_SF_DEFAULT_BUS 0 82 #define CONFIG_SF_DEFAULT_CS 0 83 #define CONFIG_SF_DEFAULT_SPEED 25000000 84 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 85 #endif 86 87 /* UART */ 88 #define CONFIG_MXC_UART 89 #define CONFIG_MXC_UART_BASE UART1_BASE 90 #define CONFIG_BAUDRATE 115200 91 92 /* USB Configs */ 93 #ifdef CONFIG_CMD_USB 94 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 95 #define CONFIG_USB_HOST_ETHER 96 #define CONFIG_USB_ETHER_ASIX 97 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 98 #define CONFIG_MXC_USB_FLAGS 0 99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 100 101 /* USB Gadget (DFU, UMS) */ 102 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 103 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 104 #define DFU_DEFAULT_POLL_TIMEOUT 300 105 106 /* USB IDs */ 107 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 108 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 109 #endif 110 #endif 111 112 /* Watchdog */ 113 #define CONFIG_HW_WATCHDOG 114 #define CONFIG_IMX_WATCHDOG 115 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 116 117 /* allow to overwrite serial and ethaddr */ 118 #define CONFIG_ENV_OVERWRITE 119 120 #define CONFIG_LOADADDR 0x12000000 121 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 122 123 #ifndef CONFIG_SPL_BUILD 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "console=ttymxc0,115200\0" \ 126 "fdt_addr=0x18000000\0" \ 127 "fdt_high=0xffffffff\0" \ 128 "initrd_high=0xffffffff\0" \ 129 "kernel_addr_r=0x10008000\0" \ 130 "fdt_addr_r=0x13000000\0" \ 131 "ramdisk_addr_r=0x18000000\0" \ 132 "scriptaddr=0x14000000\0" \ 133 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ 134 BOOTENV 135 136 #define CONFIG_BOOTCOMMAND "run distro_bootcmd" 137 138 #define BOOT_TARGET_DEVICES(func) \ 139 func(MMC, mmc, 0) \ 140 func(MMC, mmc, 2) \ 141 func(USB, usb, 1) \ 142 func(SATA, sata, 0) \ 143 func(DHCP, dhcp, na) 144 145 #include <config_distro_bootcmd.h> 146 #endif 147 148 /* Physical Memory Map */ 149 #define CONFIG_NR_DRAM_BANKS 1 150 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 151 152 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 153 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 154 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 155 156 #define CONFIG_SYS_INIT_SP_OFFSET \ 157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 158 159 #define CONFIG_SYS_INIT_SP_ADDR \ 160 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 161 162 #define CONFIG_SYS_MEMTEST_START 0x10000000 163 #define CONFIG_SYS_MEMTEST_END 0x20000000 164 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 165 166 /* Environment */ 167 #define CONFIG_ENV_SIZE (16 * 1024) 168 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 169 170 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 171 #define CONFIG_ENV_OFFSET (1024 * 1024) 172 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 173 #define CONFIG_ENV_OFFSET_REDUND \ 174 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 175 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 176 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 177 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 178 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 179 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 180 #endif 181 182 #endif /* __DH_IMX6_CONFIG_H */ 183