1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * DHCOM DH-iMX6 PDK board configuration 4 * 5 * Copyright (C) 2017 Marek Vasut <marex@denx.de> 6 */ 7 8 #ifndef __DH_IMX6_CONFIG_H 9 #define __DH_IMX6_CONFIG_H 10 11 #include <asm/arch/imx-regs.h> 12 13 #include "mx6_common.h" 14 15 /* 16 * SPI NOR layout: 17 * 0x00_0000-0x00_ffff ... U-Boot SPL 18 * 0x01_0000-0x0f_ffff ... U-Boot 19 * 0x10_0000-0x10_ffff ... U-Boot env #1 20 * 0x11_0000-0x11_ffff ... U-Boot env #2 21 * 0x12_0000-0x1f_ffff ... UNUSED 22 */ 23 24 /* SPL */ 25 #include "imx6_spl.h" /* common IMX6 SPL configuration */ 26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" 28 29 /* Miscellaneous configurable options */ 30 31 #define CONFIG_CMDLINE_TAG 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 #define CONFIG_BOUNCE_BUFFER 37 #define CONFIG_BZIP2 38 39 /* Size of malloc() pool */ 40 #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) 41 42 /* Bootcounter */ 43 #define CONFIG_SYS_BOOTCOUNT_BE 44 45 /* FEC ethernet */ 46 #define CONFIG_MII 47 #define IMX_FEC_BASE ENET_BASE_ADDR 48 #define CONFIG_FEC_XCV_TYPE RMII 49 #define CONFIG_ETHPRIME "FEC" 50 #define CONFIG_FEC_MXC_PHYADDR 0 51 #define CONFIG_ARP_TIMEOUT 200UL 52 53 /* Fuses */ 54 #ifdef CONFIG_CMD_FUSE 55 #define CONFIG_MXC_OCOTP 56 #endif 57 58 /* I2C Configs */ 59 #define CONFIG_SYS_I2C 60 #define CONFIG_SYS_I2C_MXC 61 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 62 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 63 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 64 #define CONFIG_SYS_I2C_SPEED 100000 65 66 /* MMC Configs */ 67 #define CONFIG_FSL_USDHC 68 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 69 #define CONFIG_SYS_FSL_USDHC_NUM 3 70 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ 71 72 /* SATA Configs */ 73 #ifdef CONFIG_CMD_SATA 74 #define CONFIG_SYS_SATA_MAX_DEVICE 1 75 #define CONFIG_DWC_AHSATA_PORT_ID 0 76 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 77 #define CONFIG_LBA48 78 #endif 79 80 /* SPI Flash Configs */ 81 #ifdef CONFIG_CMD_SF 82 #define CONFIG_SF_DEFAULT_BUS 0 83 #define CONFIG_SF_DEFAULT_CS 0 84 #define CONFIG_SF_DEFAULT_SPEED 25000000 85 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 86 #endif 87 88 /* UART */ 89 #define CONFIG_MXC_UART 90 #define CONFIG_MXC_UART_BASE UART1_BASE 91 #define CONFIG_BAUDRATE 115200 92 93 /* USB Configs */ 94 #ifdef CONFIG_CMD_USB 95 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 96 #define CONFIG_USB_HOST_ETHER 97 #define CONFIG_USB_ETHER_ASIX 98 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 99 #define CONFIG_MXC_USB_FLAGS 0 100 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 101 102 /* USB Gadget (DFU, UMS) */ 103 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 104 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 105 #define DFU_DEFAULT_POLL_TIMEOUT 300 106 107 /* USB IDs */ 108 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 109 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 110 #endif 111 #endif 112 113 /* Watchdog */ 114 #define CONFIG_HW_WATCHDOG 115 #define CONFIG_IMX_WATCHDOG 116 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 117 118 /* allow to overwrite serial and ethaddr */ 119 #define CONFIG_ENV_OVERWRITE 120 121 #define CONFIG_LOADADDR 0x12000000 122 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 123 124 #ifndef CONFIG_SPL_BUILD 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "console=ttymxc0,115200\0" \ 127 "fdt_addr=0x18000000\0" \ 128 "fdt_high=0xffffffff\0" \ 129 "initrd_high=0xffffffff\0" \ 130 "kernel_addr_r=0x10008000\0" \ 131 "fdt_addr_r=0x13000000\0" \ 132 "ramdisk_addr_r=0x18000000\0" \ 133 "scriptaddr=0x14000000\0" \ 134 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ 135 BOOTENV 136 137 #define CONFIG_BOOTCOMMAND "run distro_bootcmd" 138 139 #define BOOT_TARGET_DEVICES(func) \ 140 func(MMC, mmc, 0) \ 141 func(MMC, mmc, 2) \ 142 func(USB, usb, 1) \ 143 func(SATA, sata, 0) \ 144 func(DHCP, dhcp, na) 145 146 #include <config_distro_bootcmd.h> 147 #endif 148 149 /* Physical Memory Map */ 150 #define CONFIG_NR_DRAM_BANKS 1 151 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 152 153 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 154 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 155 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 156 157 #define CONFIG_SYS_INIT_SP_OFFSET \ 158 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 159 160 #define CONFIG_SYS_INIT_SP_ADDR \ 161 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 162 163 #define CONFIG_SYS_MEMTEST_START 0x10000000 164 #define CONFIG_SYS_MEMTEST_END 0x20000000 165 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 166 167 /* Environment */ 168 #define CONFIG_ENV_SIZE (16 * 1024) 169 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 170 171 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 172 #define CONFIG_ENV_OFFSET (1024 * 1024) 173 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 174 #define CONFIG_ENV_OFFSET_REDUND \ 175 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 177 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 178 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 179 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 180 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 181 #endif 182 183 #endif /* __DH_IMX6_CONFIG_H */ 184