1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 37 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 38 39 #define CONFIG_SYS_TEXT_BASE 0x80008000 40 41 #define CONFIG_SDRC /* The chip has SDRC controller */ 42 43 #include <asm/arch/cpu.h> /* get chip and board defs */ 44 #include <asm/arch/omap3.h> 45 46 /* Display CPU and Board information */ 47 #define CONFIG_DISPLAY_CPUINFO 1 48 #define CONFIG_DISPLAY_BOARDINFO 1 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #undef CONFIG_USE_IRQ /* no support for IRQs */ 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 58 #define CONFIG_SETUP_MEMORY_TAGS 1 59 #define CONFIG_INITRD_TAG 1 60 #define CONFIG_REVISION_TAG 1 61 62 #define CONFIG_OF_LIBFDT 1 63 64 /* Size of malloc() pool */ 65 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 66 /* Sector */ 67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 68 69 /* Hardware drivers */ 70 /* DM9000 */ 71 #define CONFIG_NET_RETRY_COUNT 20 72 #define CONFIG_DRIVER_DM9000 1 73 #define CONFIG_DM9000_BASE 0x2c000000 74 #define DM9000_IO CONFIG_DM9000_BASE 75 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 76 #define CONFIG_DM9000_USE_16BIT 1 77 #define CONFIG_DM9000_NO_SROM 1 78 #undef CONFIG_DM9000_DEBUG 79 80 /* NS16550 Configuration */ 81 #define CONFIG_SYS_NS16550 82 #define CONFIG_SYS_NS16550_SERIAL 83 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 84 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 85 86 /* select serial console configuration */ 87 #define CONFIG_CONS_INDEX 3 88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 89 #define CONFIG_SERIAL3 3 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 92 115200} 93 94 /* MMC */ 95 #define CONFIG_GENERIC_MMC 1 96 #define CONFIG_MMC 1 97 #define CONFIG_OMAP_HSMMC 1 98 #define CONFIG_DOS_PARTITION 1 99 100 /* I2C */ 101 #define CONFIG_HARD_I2C 1 102 #define CONFIG_SYS_I2C_SPEED 100000 103 #define CONFIG_SYS_I2C_SLAVE 1 104 #define CONFIG_SYS_I2C_BUS 0 105 #define CONFIG_SYS_I2C_BUS_SELECT 1 106 #define CONFIG_DRIVER_OMAP34XX_I2C 1 107 108 /* TWL4030 */ 109 #define CONFIG_TWL4030_POWER 1 110 #define CONFIG_TWL4030_LED 1 111 112 /* Board NAND Info */ 113 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 114 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 115 #define MTDIDS_DEFAULT "nand0=nand" 116 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 117 "512k(x-loader)," \ 118 "1920k(u-boot)," \ 119 "128k(u-boot-env)," \ 120 "4m(kernel)," \ 121 "-(fs)" 122 123 #define CONFIG_NAND_OMAP_GPMC 124 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 125 /* to access nand */ 126 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 127 /* to access nand at */ 128 /* CS0 */ 129 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 130 131 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 132 /* devices */ 133 #define CONFIG_JFFS2_NAND 134 /* nand device jffs2 lives on */ 135 #define CONFIG_JFFS2_DEV "nand0" 136 /* start of jffs2 partition */ 137 #define CONFIG_JFFS2_PART_OFFSET 0x680000 138 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 139 /* partition */ 140 141 /* commands to include */ 142 #include <config_cmd_default.h> 143 144 #define CONFIG_CMD_DHCP /* DHCP support */ 145 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 146 #define CONFIG_CMD_FAT /* FAT support */ 147 #define CONFIG_CMD_I2C /* I2C serial bus support */ 148 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 149 #define CONFIG_CMD_MMC /* MMC support */ 150 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 151 #define CONFIG_CMD_NAND /* NAND support */ 152 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 153 154 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 155 #undef CONFIG_CMD_IMI /* iminfo */ 156 157 /* BOOTP/DHCP options */ 158 #define CONFIG_BOOTP_SUBNETMASK 159 #define CONFIG_BOOTP_GATEWAY 160 #define CONFIG_BOOTP_HOSTNAME 161 #define CONFIG_BOOTP_NISDOMAIN 162 #define CONFIG_BOOTP_BOOTPATH 163 #define CONFIG_BOOTP_BOOTFILESIZE 164 #define CONFIG_BOOTP_DNS 165 #define CONFIG_BOOTP_DNS2 166 #define CONFIG_BOOTP_SEND_HOSTNAME 167 #define CONFIG_BOOTP_NTPSERVER 168 #define CONFIG_BOOTP_TIMEOFFSET 169 #undef CONFIG_BOOTP_VENDOREX 170 171 /* Environment information */ 172 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 173 174 #define CONFIG_BOOTDELAY 3 175 176 #define CONFIG_EXTRA_ENV_SETTINGS \ 177 "loadaddr=0x82000000\0" \ 178 "console=ttyO2,115200n8\0" \ 179 "mmcdev=0\0" \ 180 "vram=12M\0" \ 181 "dvimode=1024x768MR-16@60\0" \ 182 "defaultdisplay=dvi\0" \ 183 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 184 "kernelopts=rw\0" \ 185 "commonargs=" \ 186 "setenv bootargs console=${console} " \ 187 "vram=${vram} " \ 188 "omapfb.mode=dvi:${dvimode} " \ 189 "omapdss.def_disp=${defaultdisplay}\0" \ 190 "mmcargs=" \ 191 "run commonargs; " \ 192 "setenv bootargs ${bootargs} " \ 193 "root=/dev/mmcblk0p2 " \ 194 "${kernelopts}\0" \ 195 "nandargs=" \ 196 "run commonargs; " \ 197 "setenv bootargs ${bootargs} " \ 198 "omapfb.mode=dvi:${dvimode} " \ 199 "omapdss.def_disp=${defaultdisplay} " \ 200 "root=/dev/mtdblock4 " \ 201 "rootfstype=jffs2 " \ 202 "${kernelopts}\0" \ 203 "netargs=" \ 204 "run commonargs; " \ 205 "setenv bootargs ${bootargs} " \ 206 "root=/dev/nfs " \ 207 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 208 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 209 "${kernelopts} " \ 210 "dnsip1=${dnsip} " \ 211 "dnsip2=${dnsip2}\0" \ 212 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 213 "bootscript=echo Running bootscript from mmc ...; " \ 214 "source ${loadaddr}\0" \ 215 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 216 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 217 "mmcboot=echo Booting from mmc ...; " \ 218 "run mmcargs; " \ 219 "bootm ${loadaddr}\0" \ 220 "nandboot=echo Booting from nand ...; " \ 221 "run nandargs; " \ 222 "nand read ${loadaddr} 280000 400000; " \ 223 "bootm ${loadaddr}\0" \ 224 "netboot=echo Booting from network ...; " \ 225 "dhcp ${loadaddr}; " \ 226 "run netargs; " \ 227 "bootm ${loadaddr}\0" \ 228 "autoboot=if mmc rescan ${mmcdev}; then " \ 229 "if run loadbootscript; then " \ 230 "run bootscript; " \ 231 "else " \ 232 "if run loaduimage; then " \ 233 "run mmcboot; " \ 234 "else run nandboot; " \ 235 "fi; " \ 236 "fi; " \ 237 "else run nandboot; fi\0" 238 239 240 #define CONFIG_BOOTCOMMAND "run autoboot" 241 242 /* Miscellaneous configurable options */ 243 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 244 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 245 #define CONFIG_AUTO_COMPLETE 1 246 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 247 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 248 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 249 /* Print Buffer Size */ 250 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 251 sizeof(CONFIG_SYS_PROMPT) + 16) 252 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 253 254 /* Boot Argument Buffer Size */ 255 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 256 257 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 258 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 259 0x01000000) /* 16MB */ 260 261 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 262 263 /* 264 * OMAP3 has 12 GP timers, they can be driven by the system clock 265 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 266 * This rate is divided by a local divisor. 267 */ 268 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 269 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 270 #define CONFIG_SYS_HZ 1000 271 272 /* The stack sizes are set up in start.S using the settings below */ 273 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 274 275 /* Physical Memory Map */ 276 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 277 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 278 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 279 280 /* NAND and environment organization */ 281 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 282 283 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 284 285 #define CONFIG_ENV_IS_IN_NAND 1 286 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 287 288 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 289 290 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 291 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 292 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 293 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 294 CONFIG_SYS_INIT_RAM_SIZE - \ 295 GENERATED_GBL_DATA_SIZE) 296 297 /* SRAM config */ 298 #define CONFIG_SYS_SRAM_START 0x40200000 299 #define CONFIG_SYS_SRAM_SIZE 0x10000 300 301 /* Defines for SPL */ 302 #define CONFIG_SPL 303 #define CONFIG_SPL_NAND_SIMPLE 304 305 #define CONFIG_SPL_LIBCOMMON_SUPPORT 306 #define CONFIG_SPL_LIBDISK_SUPPORT 307 #define CONFIG_SPL_BOARD_INIT 308 #define CONFIG_SPL_I2C_SUPPORT 309 #define CONFIG_SPL_LIBGENERIC_SUPPORT 310 #define CONFIG_SPL_SERIAL_SUPPORT 311 #define CONFIG_SPL_POWER_SUPPORT 312 #define CONFIG_SPL_NAND_SUPPORT 313 #define CONFIG_SPL_MMC_SUPPORT 314 #define CONFIG_SPL_FAT_SUPPORT 315 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 316 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 317 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 318 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 319 320 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 321 #define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ 322 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 323 324 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 325 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 326 327 /* NAND boot config */ 328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 329 #define CONFIG_SYS_NAND_PAGE_COUNT 64 330 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 331 #define CONFIG_SYS_NAND_OOBSIZE 64 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 334 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 335 10, 11, 12, 13} 336 337 #define CONFIG_SYS_NAND_ECCSIZE 512 338 #define CONFIG_SYS_NAND_ECCBYTES 3 339 340 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ 341 CONFIG_SYS_NAND_ECCSIZE) 342 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ 343 CONFIG_SYS_NAND_ECCSTEPS) 344 345 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 346 347 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 348 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 349 350 #define CONFIG_SYS_SPL_MALLOC_START 0x80108000 351 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 352 353 #endif /* __CONFIG_H */ 354