xref: /openbmc/u-boot/include/configs/devkit8000.h (revision dc7685e2)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2006-2008
4  * Texas Instruments.
5  * Richard Woodruff <r-woodruff2@ti.com>
6  * Syed Mohammed Khasim <x0khasim@ti.com>
7  *
8  * (C) Copyright 2009
9  * Frederik Kriewitz <frederik@kriewitz.eu>
10  *
11  * Configuration settings for the DevKit8000 board.
12  */
13 
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16 
17 /* High Level Configuration Options */
18 #define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000
19 
20 /*
21  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
22  * 64 bytes before this address should be set aside for u-boot.img's
23  * header. That is 0x800FFFC0--0x80100000 should not be used for any
24  * other needs.
25  */
26 
27 #define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
28 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
29 
30 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
31 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
32 
33 /*  Physical Memory Map  */
34 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
35 
36 #include <configs/ti_omap3_common.h>
37 
38 #define CONFIG_MISC_INIT_R
39 
40 #define CONFIG_REVISION_TAG		1
41 
42 /* Size of malloc() pool */
43 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
44 						/* Sector */
45 #undef CONFIG_SYS_MALLOC_LEN
46 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
47 
48 /* Hardware drivers */
49 /* DM9000 */
50 #define CONFIG_NET_RETRY_COUNT		20
51 #define	CONFIG_DRIVER_DM9000		1
52 #define	CONFIG_DM9000_BASE		0x2c000000
53 #define	DM9000_IO			CONFIG_DM9000_BASE
54 #define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
55 #define	CONFIG_DM9000_USE_16BIT		1
56 #define CONFIG_DM9000_NO_SROM		1
57 #undef	CONFIG_DM9000_DEBUG
58 
59 /* TWL4030 */
60 #define CONFIG_TWL4030_LED		1
61 
62 /* Board NAND Info */
63 #define CONFIG_JFFS2_NAND
64 /* nand device jffs2 lives on */
65 #define CONFIG_JFFS2_DEV		"nand0"
66 /* start of jffs2 partition */
67 #define CONFIG_JFFS2_PART_OFFSET	0x680000
68 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
69 							/* partition */
70 
71 /* BOOTP/DHCP options */
72 #define CONFIG_BOOTP_NISDOMAIN
73 #define CONFIG_BOOTP_BOOTFILESIZE
74 #define CONFIG_BOOTP_DNS2
75 #define CONFIG_BOOTP_SEND_HOSTNAME
76 #define CONFIG_BOOTP_TIMEOFFSET
77 #undef CONFIG_BOOTP_VENDOREX
78 
79 /* Environment information */
80 #define CONFIG_EXTRA_ENV_SETTINGS \
81 	"loadaddr=0x82000000\0" \
82 	"console=ttyO2,115200n8\0" \
83 	"mmcdev=0\0" \
84 	"vram=12M\0" \
85 	"dvimode=1024x768MR-16@60\0" \
86 	"defaultdisplay=dvi\0" \
87 	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
88 	"kernelopts=rw\0" \
89 	"commonargs=" \
90 		"setenv bootargs console=${console} " \
91 		"vram=${vram} " \
92 		"omapfb.mode=dvi:${dvimode} " \
93 		"omapdss.def_disp=${defaultdisplay}\0" \
94 	"mmcargs=" \
95 		"run commonargs; " \
96 		"setenv bootargs ${bootargs} " \
97 		"root=/dev/mmcblk0p2 " \
98 		"rootwait " \
99 		"${kernelopts}\0" \
100 	"nandargs=" \
101 		"run commonargs; " \
102 		"setenv bootargs ${bootargs} " \
103 		"omapfb.mode=dvi:${dvimode} " \
104 		"omapdss.def_disp=${defaultdisplay} " \
105 		"root=/dev/mtdblock4 " \
106 		"rootfstype=jffs2 " \
107 		"${kernelopts}\0" \
108 	"netargs=" \
109 		"run commonargs; " \
110 		"setenv bootargs ${bootargs} " \
111 		"root=/dev/nfs " \
112 		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
113 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
114 		"${kernelopts} " \
115 		"dnsip1=${dnsip} " \
116 		"dnsip2=${dnsip2}\0" \
117 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
118 	"bootscript=echo Running bootscript from mmc ...; " \
119 		"source ${loadaddr}\0" \
120 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
121 	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
122 	"mmcboot=echo Booting from mmc ...; " \
123 		"run mmcargs; " \
124 		"bootm ${loadaddr}\0" \
125 	"nandboot=echo Booting from nand ...; " \
126 		"run nandargs; " \
127 		"nand read ${loadaddr} 280000 400000; " \
128 		"bootm ${loadaddr}\0" \
129 	"netboot=echo Booting from network ...; " \
130 		"dhcp ${loadaddr}; " \
131 		"run netargs; " \
132 		"bootm ${loadaddr}\0" \
133 	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
134 			"if run loadbootscript; then " \
135 				"run bootscript; " \
136 			"else " \
137 				"if run loaduimage; then " \
138 					"run mmcboot; " \
139 				"else run nandboot; " \
140 				"fi; " \
141 			"fi; " \
142 		"else run nandboot; fi\0"
143 
144 #define CONFIG_BOOTCOMMAND "run autoboot"
145 
146 /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
148 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
149 					0x01000000) /* 16MB */
150 
151 /* NAND and environment organization  */
152 
153 #define CONFIG_ENV_OFFSET		0x260000
154 
155 /* SRAM config */
156 #define CONFIG_SYS_SRAM_START              0x40200000
157 #define CONFIG_SYS_SRAM_SIZE               0x10000
158 
159 /* Defines for SPL */
160 
161 #undef CONFIG_SPL_TEXT_BASE
162 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
163 
164 /* NAND boot config */
165 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
166 #define CONFIG_SYS_NAND_PAGE_COUNT	64
167 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
168 #define CONFIG_SYS_NAND_OOBSIZE		64
169 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
171 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
172 						10, 11, 12, 13}
173 
174 #define CONFIG_SYS_NAND_ECCSIZE		512
175 #define CONFIG_SYS_NAND_ECCBYTES	3
176 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
177 
178 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
179 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
180 
181 /* SPL OS boot options */
182 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
183 
184 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
185 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
186 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
187 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
188 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
189 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
190 
191 #undef CONFIG_SYS_SPL_ARGS_ADDR
192 #define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
193 
194 #endif /* __CONFIG_H */
195