1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 36 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 39 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap3.h> 43 44 /* Display CPU and Board information */ 45 #define CONFIG_DISPLAY_CPUINFO 1 46 #define CONFIG_DISPLAY_BOARDINFO 1 47 48 /* Clock Defines */ 49 #define V_OSCK 26000000 /* Clock output from T2 */ 50 #define V_SCLK (V_OSCK >> 1) 51 52 #undef CONFIG_USE_IRQ /* no support for IRQs */ 53 #define CONFIG_MISC_INIT_R 54 55 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 56 #define CONFIG_SETUP_MEMORY_TAGS 1 57 #define CONFIG_INITRD_TAG 1 58 #define CONFIG_REVISION_TAG 1 59 60 /* Size of malloc() pool */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 62 /* Sector */ 63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 64 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 65 /* initial data */ 66 67 /* Hardware drivers */ 68 69 /* DDR - I use Micron DDR */ 70 #define CONFIG_OMAP3_MICRON_DDR 1 71 72 /* DM9000 */ 73 #define CONFIG_NET_MULTI 1 74 #define CONFIG_NET_RETRY_COUNT 20 75 #define CONFIG_DRIVER_DM9000 1 76 #define CONFIG_DM9000_BASE 0x2c000000 77 #define DM9000_IO CONFIG_DM9000_BASE 78 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 79 #define CONFIG_DM9000_USE_16BIT 1 80 #define CONFIG_DM9000_NO_SROM 1 81 #undef CONFIG_DM9000_DEBUG 82 83 /* NS16550 Configuration */ 84 #define CONFIG_SYS_NS16550 85 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 87 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 88 89 /* select serial console configuration */ 90 #define CONFIG_CONS_INDEX 3 91 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 92 #define CONFIG_SERIAL3 3 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 97 /* MMC */ 98 #define CONFIG_MMC 1 99 #define CONFIG_OMAP3_MMC 1 100 #define CONFIG_DOS_PARTITION 1 101 102 /* I2C */ 103 #define CONFIG_HARD_I2C 1 104 #define CONFIG_SYS_I2C_SPEED 100000 105 #define CONFIG_SYS_I2C_SLAVE 1 106 #define CONFIG_SYS_I2C_BUS 0 107 #define CONFIG_SYS_I2C_BUS_SELECT 1 108 #define CONFIG_DRIVER_OMAP34XX_I2C 1 109 110 /* TWL4030 */ 111 #define CONFIG_TWL4030_POWER 1 112 #define CONFIG_TWL4030_LED 1 113 114 /* Board NAND Info */ 115 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 116 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 117 #define MTDIDS_DEFAULT "nand0=nand" 118 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 119 "512k(x-loader)," \ 120 "1920k(u-boot)," \ 121 "128k(u-boot-env)," \ 122 "4m(kernel)," \ 123 "-(fs)" 124 125 #define CONFIG_NAND_OMAP_GPMC 126 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 127 /* to access nand */ 128 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 129 /* to access nand at */ 130 /* CS0 */ 131 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 132 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 134 /* devices */ 135 #define CONFIG_JFFS2_NAND 136 /* nand device jffs2 lives on */ 137 #define CONFIG_JFFS2_DEV "nand0" 138 /* start of jffs2 partition */ 139 #define CONFIG_JFFS2_PART_OFFSET 0x680000 140 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 141 /* partition */ 142 143 /* commands to include */ 144 #include <config_cmd_default.h> 145 146 #define CONFIG_CMD_DHCP /* DHCP support */ 147 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 148 #define CONFIG_CMD_FAT /* FAT support */ 149 #define CONFIG_CMD_I2C /* I2C serial bus support */ 150 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 151 #define CONFIG_CMD_MMC /* MMC support */ 152 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 153 #define CONFIG_CMD_NAND /* NAND support */ 154 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 155 156 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 157 #undef CONFIG_CMD_IMI /* iminfo */ 158 159 /* BOOTP/DHCP options */ 160 #define CONFIG_BOOTP_SUBNETMASK 161 #define CONFIG_BOOTP_GATEWAY 162 #define CONFIG_BOOTP_HOSTNAME 163 #define CONFIG_BOOTP_NISDOMAIN 164 #define CONFIG_BOOTP_BOOTPATH 165 #define CONFIG_BOOTP_BOOTFILESIZE 166 #define CONFIG_BOOTP_DNS 167 #define CONFIG_BOOTP_DNS2 168 #define CONFIG_BOOTP_SEND_HOSTNAME 169 #define CONFIG_BOOTP_NTPSERVER 170 #define CONFIG_BOOTP_TIMEOFFSET 171 #undef CONFIG_BOOTP_VENDOREX 172 173 /* Environment information */ 174 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 175 176 #define CONFIG_BOOTDELAY 3 177 178 #define CONFIG_EXTRA_ENV_SETTINGS \ 179 "loadaddr=0x82000000\0" \ 180 "console=ttyS2,115200n8\0" \ 181 "vram=12M\0" \ 182 "dvimode=1024x768MR-16@60\0" \ 183 "defaultdisplay=dvi\0" \ 184 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 185 "kernelopts=rw\0" \ 186 "commonargs=" \ 187 "setenv bootargs console=${console} " \ 188 "vram=${vram} " \ 189 "omapfb.mode=dvi:${dvimode} " \ 190 "omapdss.def_disp=${defaultdisplay}\0" \ 191 "mmcargs=" \ 192 "run commonargs; " \ 193 "setenv bootargs ${bootargs} " \ 194 "root=/dev/mmcblk0p2 " \ 195 "${kernelopts}\0" \ 196 "nandargs=" \ 197 "run commonargs; " \ 198 "setenv bootargs ${bootargs} " \ 199 "omapfb.mode=dvi:${dvimode} " \ 200 "omapdss.def_disp=${defaultdisplay} " \ 201 "root=/dev/mtdblock4 " \ 202 "rootfstype=jffs2 " \ 203 "${kernelopts}\0" \ 204 "netargs=" \ 205 "run commonargs; " \ 206 "setenv bootargs ${bootargs} " \ 207 "root=/dev/nfs " \ 208 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 209 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 210 "${kernelopts} " \ 211 "dnsip1=${dnsip} " \ 212 "dnsip2=${dnsip2}\0" \ 213 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 214 "bootscript=echo Running bootscript from mmc ...; " \ 215 "source ${loadaddr}\0" \ 216 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 217 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 218 "mmcboot=echo Booting from mmc ...; " \ 219 "run mmcargs; " \ 220 "bootm ${loadaddr}\0" \ 221 "nandboot=echo Booting from nand ...; " \ 222 "run nandargs; " \ 223 "nand read ${loadaddr} 280000 400000; " \ 224 "bootm ${loadaddr}\0" \ 225 "netboot=echo Booting from network ...; " \ 226 "dhcp ${loadaddr}; " \ 227 "run netargs; " \ 228 "bootm ${loadaddr}\0" \ 229 "autoboot=if mmc init 0; then " \ 230 "if run loadbootscript; then " \ 231 "run bootscript; " \ 232 "else " \ 233 "if run loaduimage; then " \ 234 "run mmcboot; " \ 235 "else run nandboot; " \ 236 "fi; " \ 237 "fi; " \ 238 "else run nandboot; fi\0" 239 240 241 #define CONFIG_BOOTCOMMAND "run autoboot" 242 243 /* Miscellaneous configurable options */ 244 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 245 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 246 #define CONFIG_AUTO_COMPLETE 1 247 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 248 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 249 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 250 /* Print Buffer Size */ 251 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 252 sizeof(CONFIG_SYS_PROMPT) + 16) 253 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 254 255 /* Boot Argument Buffer Size */ 256 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 257 258 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 259 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 260 0x01000000) /* 16MB */ 261 262 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 263 264 /* 265 * OMAP3 has 12 GP timers, they can be driven by the system clock 266 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 267 * This rate is divided by a local divisor. 268 */ 269 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 270 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 271 #define CONFIG_SYS_HZ 1000 272 273 /* The stack sizes are set up in start.S using the settings below */ 274 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 275 #ifdef CONFIG_USE_IRQ 276 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 277 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 278 #endif 279 280 /* Physical Memory Map */ 281 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 282 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 283 #define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ 284 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 285 286 /* SDRAM Bank Allocation method */ 287 #define SDRC_R_B_C 1 288 289 /* NAND and environment organization */ 290 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 291 292 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 293 294 #define CONFIG_ENV_IS_IN_NAND 1 295 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 296 297 #define CONFIG_ENV_OFFSET boot_flash_off 298 299 #ifndef __ASSEMBLY__ 300 extern struct gpmc *gpmc_cfg; 301 extern unsigned int boot_flash_base; 302 extern volatile unsigned int boot_flash_env_addr; 303 extern unsigned int boot_flash_off; 304 extern unsigned int boot_flash_sec; 305 extern unsigned int boot_flash_type; 306 #endif 307 308 #endif /* __CONFIG_H */ 309