1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 37 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 38 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 39 /* 40 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 41 * 64 bytes before this address should be set aside for u-boot.img's 42 * header. That is 0x800FFFC0--0x80100000 should not be used for any 43 * other needs. 44 */ 45 #define CONFIG_SYS_TEXT_BASE 0x80100000 46 47 #define CONFIG_SDRC /* The chip has SDRC controller */ 48 49 #include <asm/arch/cpu.h> /* get chip and board defs */ 50 #include <asm/arch/omap3.h> 51 52 /* Display CPU and Board information */ 53 #define CONFIG_DISPLAY_CPUINFO 1 54 #define CONFIG_DISPLAY_BOARDINFO 1 55 56 /* Clock Defines */ 57 #define V_OSCK 26000000 /* Clock output from T2 */ 58 #define V_SCLK (V_OSCK >> 1) 59 60 #undef CONFIG_USE_IRQ /* no support for IRQs */ 61 #define CONFIG_MISC_INIT_R 62 63 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 64 #define CONFIG_SETUP_MEMORY_TAGS 1 65 #define CONFIG_INITRD_TAG 1 66 #define CONFIG_REVISION_TAG 1 67 68 #define CONFIG_OF_LIBFDT 1 69 70 /* Size of malloc() pool */ 71 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 72 /* Sector */ 73 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 74 75 /* Hardware drivers */ 76 /* DM9000 */ 77 #define CONFIG_NET_RETRY_COUNT 20 78 #define CONFIG_DRIVER_DM9000 1 79 #define CONFIG_DM9000_BASE 0x2c000000 80 #define DM9000_IO CONFIG_DM9000_BASE 81 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 82 #define CONFIG_DM9000_USE_16BIT 1 83 #define CONFIG_DM9000_NO_SROM 1 84 #undef CONFIG_DM9000_DEBUG 85 86 /* NS16550 Configuration */ 87 #define CONFIG_SYS_NS16550 88 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 90 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 91 92 /* select serial console configuration */ 93 #define CONFIG_CONS_INDEX 3 94 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 95 #define CONFIG_SERIAL3 3 96 #define CONFIG_BAUDRATE 115200 97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 98 115200} 99 100 /* MMC */ 101 #define CONFIG_GENERIC_MMC 1 102 #define CONFIG_MMC 1 103 #define CONFIG_OMAP_HSMMC 1 104 #define CONFIG_DOS_PARTITION 1 105 106 /* I2C */ 107 #define CONFIG_HARD_I2C 1 108 #define CONFIG_SYS_I2C_SPEED 100000 109 #define CONFIG_SYS_I2C_SLAVE 1 110 #define CONFIG_SYS_I2C_BUS 0 111 #define CONFIG_SYS_I2C_BUS_SELECT 1 112 #define CONFIG_DRIVER_OMAP34XX_I2C 1 113 114 /* TWL4030 */ 115 #define CONFIG_TWL4030_POWER 1 116 #define CONFIG_TWL4030_LED 1 117 118 /* Board NAND Info */ 119 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 120 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 121 #define MTDIDS_DEFAULT "nand0=nand" 122 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 123 "512k(x-loader)," \ 124 "1920k(u-boot)," \ 125 "128k(u-boot-env)," \ 126 "4m(kernel)," \ 127 "-(fs)" 128 129 #define CONFIG_NAND_OMAP_GPMC 130 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 131 /* to access nand */ 132 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 133 /* to access nand at */ 134 /* CS0 */ 135 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 136 137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 138 /* devices */ 139 #define CONFIG_JFFS2_NAND 140 /* nand device jffs2 lives on */ 141 #define CONFIG_JFFS2_DEV "nand0" 142 /* start of jffs2 partition */ 143 #define CONFIG_JFFS2_PART_OFFSET 0x680000 144 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 145 /* partition */ 146 147 /* commands to include */ 148 #include <config_cmd_default.h> 149 150 #define CONFIG_CMD_DHCP /* DHCP support */ 151 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 152 #define CONFIG_CMD_FAT /* FAT support */ 153 #define CONFIG_CMD_I2C /* I2C serial bus support */ 154 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 155 #define CONFIG_CMD_MMC /* MMC support */ 156 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 157 #define CONFIG_CMD_NAND /* NAND support */ 158 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 159 160 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 161 #undef CONFIG_CMD_IMI /* iminfo */ 162 163 /* BOOTP/DHCP options */ 164 #define CONFIG_BOOTP_SUBNETMASK 165 #define CONFIG_BOOTP_GATEWAY 166 #define CONFIG_BOOTP_HOSTNAME 167 #define CONFIG_BOOTP_NISDOMAIN 168 #define CONFIG_BOOTP_BOOTPATH 169 #define CONFIG_BOOTP_BOOTFILESIZE 170 #define CONFIG_BOOTP_DNS 171 #define CONFIG_BOOTP_DNS2 172 #define CONFIG_BOOTP_SEND_HOSTNAME 173 #define CONFIG_BOOTP_NTPSERVER 174 #define CONFIG_BOOTP_TIMEOFFSET 175 #undef CONFIG_BOOTP_VENDOREX 176 177 /* Environment information */ 178 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 179 180 #define CONFIG_BOOTDELAY 3 181 182 #define CONFIG_EXTRA_ENV_SETTINGS \ 183 "loadaddr=0x82000000\0" \ 184 "console=ttyO2,115200n8\0" \ 185 "mmcdev=0\0" \ 186 "vram=12M\0" \ 187 "dvimode=1024x768MR-16@60\0" \ 188 "defaultdisplay=dvi\0" \ 189 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 190 "kernelopts=rw\0" \ 191 "commonargs=" \ 192 "setenv bootargs console=${console} " \ 193 "vram=${vram} " \ 194 "omapfb.mode=dvi:${dvimode} " \ 195 "omapdss.def_disp=${defaultdisplay}\0" \ 196 "mmcargs=" \ 197 "run commonargs; " \ 198 "setenv bootargs ${bootargs} " \ 199 "root=/dev/mmcblk0p2 " \ 200 "${kernelopts}\0" \ 201 "nandargs=" \ 202 "run commonargs; " \ 203 "setenv bootargs ${bootargs} " \ 204 "omapfb.mode=dvi:${dvimode} " \ 205 "omapdss.def_disp=${defaultdisplay} " \ 206 "root=/dev/mtdblock4 " \ 207 "rootfstype=jffs2 " \ 208 "${kernelopts}\0" \ 209 "netargs=" \ 210 "run commonargs; " \ 211 "setenv bootargs ${bootargs} " \ 212 "root=/dev/nfs " \ 213 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 214 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 215 "${kernelopts} " \ 216 "dnsip1=${dnsip} " \ 217 "dnsip2=${dnsip2}\0" \ 218 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 219 "bootscript=echo Running bootscript from mmc ...; " \ 220 "source ${loadaddr}\0" \ 221 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 222 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 223 "mmcboot=echo Booting from mmc ...; " \ 224 "run mmcargs; " \ 225 "bootm ${loadaddr}\0" \ 226 "nandboot=echo Booting from nand ...; " \ 227 "run nandargs; " \ 228 "nand read ${loadaddr} 280000 400000; " \ 229 "bootm ${loadaddr}\0" \ 230 "netboot=echo Booting from network ...; " \ 231 "dhcp ${loadaddr}; " \ 232 "run netargs; " \ 233 "bootm ${loadaddr}\0" \ 234 "autoboot=if mmc rescan ${mmcdev}; then " \ 235 "if run loadbootscript; then " \ 236 "run bootscript; " \ 237 "else " \ 238 "if run loaduimage; then " \ 239 "run mmcboot; " \ 240 "else run nandboot; " \ 241 "fi; " \ 242 "fi; " \ 243 "else run nandboot; fi\0" 244 245 246 #define CONFIG_BOOTCOMMAND "run autoboot" 247 248 /* Miscellaneous configurable options */ 249 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 250 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 251 #define CONFIG_AUTO_COMPLETE 1 252 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 253 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 254 /* Print Buffer Size */ 255 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 256 sizeof(CONFIG_SYS_PROMPT) + 16) 257 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 258 259 /* Boot Argument Buffer Size */ 260 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 261 262 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 263 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 264 0x01000000) /* 16MB */ 265 266 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 267 268 /* 269 * OMAP3 has 12 GP timers, they can be driven by the system clock 270 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 271 * This rate is divided by a local divisor. 272 */ 273 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 274 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 275 #define CONFIG_SYS_HZ 1000 276 277 /* The stack sizes are set up in start.S using the settings below */ 278 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 279 280 /* Physical Memory Map */ 281 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 282 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 283 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 284 285 /* NAND and environment organization */ 286 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 287 288 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 289 290 #define CONFIG_ENV_IS_IN_NAND 1 291 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 292 293 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 294 295 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 296 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 297 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 298 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 299 CONFIG_SYS_INIT_RAM_SIZE - \ 300 GENERATED_GBL_DATA_SIZE) 301 302 /* SRAM config */ 303 #define CONFIG_SYS_SRAM_START 0x40200000 304 #define CONFIG_SYS_SRAM_SIZE 0x10000 305 306 /* Defines for SPL */ 307 #define CONFIG_SPL 308 #define CONFIG_SPL_NAND_SIMPLE 309 310 #define CONFIG_SPL_LIBCOMMON_SUPPORT 311 #define CONFIG_SPL_LIBDISK_SUPPORT 312 #define CONFIG_SPL_BOARD_INIT 313 #define CONFIG_SPL_I2C_SUPPORT 314 #define CONFIG_SPL_LIBGENERIC_SUPPORT 315 #define CONFIG_SPL_SERIAL_SUPPORT 316 #define CONFIG_SPL_POWER_SUPPORT 317 #define CONFIG_SPL_NAND_SUPPORT 318 #define CONFIG_SPL_MMC_SUPPORT 319 #define CONFIG_SPL_FAT_SUPPORT 320 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 321 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 322 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 323 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 324 325 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 326 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 327 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 328 329 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 330 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 331 332 /* NAND boot config */ 333 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 334 #define CONFIG_SYS_NAND_PAGE_COUNT 64 335 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 336 #define CONFIG_SYS_NAND_OOBSIZE 64 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 338 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 339 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 340 10, 11, 12, 13} 341 342 #define CONFIG_SYS_NAND_ECCSIZE 512 343 #define CONFIG_SYS_NAND_ECCBYTES 3 344 345 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 346 347 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 348 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 349 350 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 351 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 352 353 /* SPL OS boot options */ 354 #define CONFIG_SPL_OS_BOOT 355 #define CONFIG_SPL_OS_BOOT_KEY 26 356 357 #define CONFIG_CMD_SPL 358 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 359 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 360 0x400000) 361 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 362 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 363 364 #endif /* __CONFIG_H */ 365