1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* High Level Configuration Options */ 19 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 20 21 /* 22 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 23 * 64 bytes before this address should be set aside for u-boot.img's 24 * header. That is 0x800FFFC0--0x80100000 should not be used for any 25 * other needs. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x80100000 28 29 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 30 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 31 32 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 34 35 #define CONFIG_NAND 36 37 /* Physical Memory Map */ 38 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 39 40 #include <configs/ti_omap3_common.h> 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_REVISION_TAG 1 45 46 /* Size of malloc() pool */ 47 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 48 /* Sector */ 49 #undef CONFIG_SYS_MALLOC_LEN 50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 51 52 /* Hardware drivers */ 53 /* DM9000 */ 54 #define CONFIG_NET_RETRY_COUNT 20 55 #define CONFIG_DRIVER_DM9000 1 56 #define CONFIG_DM9000_BASE 0x2c000000 57 #define DM9000_IO CONFIG_DM9000_BASE 58 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 59 #define CONFIG_DM9000_USE_16BIT 1 60 #define CONFIG_DM9000_NO_SROM 1 61 #undef CONFIG_DM9000_DEBUG 62 63 /* SPI */ 64 #undef CONFIG_SPI 65 #undef CONFIG_OMAP3_SPI 66 67 /* I2C */ 68 #undef CONFIG_SYS_I2C_OMAP24XX 69 #define CONFIG_SYS_I2C_OMAP34XX 70 71 /* TWL4030 */ 72 #define CONFIG_TWL4030_LED 1 73 74 /* Board NAND Info */ 75 #define MTDIDS_DEFAULT "nand0=nand" 76 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 77 "512k(x-loader)," \ 78 "1920k(u-boot)," \ 79 "128k(u-boot-env)," \ 80 "4m(kernel)," \ 81 "-(fs)" 82 83 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 84 /* to access nand */ 85 #define CONFIG_JFFS2_NAND 86 /* nand device jffs2 lives on */ 87 #define CONFIG_JFFS2_DEV "nand0" 88 /* start of jffs2 partition */ 89 #define CONFIG_JFFS2_PART_OFFSET 0x680000 90 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 91 /* partition */ 92 93 #undef CONFIG_SUPPORT_RAW_INITRD 94 95 /* BOOTP/DHCP options */ 96 #define CONFIG_BOOTP_SUBNETMASK 97 #define CONFIG_BOOTP_GATEWAY 98 #define CONFIG_BOOTP_HOSTNAME 99 #define CONFIG_BOOTP_NISDOMAIN 100 #define CONFIG_BOOTP_BOOTPATH 101 #define CONFIG_BOOTP_BOOTFILESIZE 102 #define CONFIG_BOOTP_DNS 103 #define CONFIG_BOOTP_DNS2 104 #define CONFIG_BOOTP_SEND_HOSTNAME 105 #define CONFIG_BOOTP_NTPSERVER 106 #define CONFIG_BOOTP_TIMEOFFSET 107 #undef CONFIG_BOOTP_VENDOREX 108 109 /* Environment information */ 110 #define CONFIG_EXTRA_ENV_SETTINGS \ 111 "loadaddr=0x82000000\0" \ 112 "console=ttyO2,115200n8\0" \ 113 "mmcdev=0\0" \ 114 "vram=12M\0" \ 115 "dvimode=1024x768MR-16@60\0" \ 116 "defaultdisplay=dvi\0" \ 117 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 118 "kernelopts=rw\0" \ 119 "commonargs=" \ 120 "setenv bootargs console=${console} " \ 121 "vram=${vram} " \ 122 "omapfb.mode=dvi:${dvimode} " \ 123 "omapdss.def_disp=${defaultdisplay}\0" \ 124 "mmcargs=" \ 125 "run commonargs; " \ 126 "setenv bootargs ${bootargs} " \ 127 "root=/dev/mmcblk0p2 " \ 128 "rootwait " \ 129 "${kernelopts}\0" \ 130 "nandargs=" \ 131 "run commonargs; " \ 132 "setenv bootargs ${bootargs} " \ 133 "omapfb.mode=dvi:${dvimode} " \ 134 "omapdss.def_disp=${defaultdisplay} " \ 135 "root=/dev/mtdblock4 " \ 136 "rootfstype=jffs2 " \ 137 "${kernelopts}\0" \ 138 "netargs=" \ 139 "run commonargs; " \ 140 "setenv bootargs ${bootargs} " \ 141 "root=/dev/nfs " \ 142 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 143 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 144 "${kernelopts} " \ 145 "dnsip1=${dnsip} " \ 146 "dnsip2=${dnsip2}\0" \ 147 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 148 "bootscript=echo Running bootscript from mmc ...; " \ 149 "source ${loadaddr}\0" \ 150 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 151 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 152 "mmcboot=echo Booting from mmc ...; " \ 153 "run mmcargs; " \ 154 "bootm ${loadaddr}\0" \ 155 "nandboot=echo Booting from nand ...; " \ 156 "run nandargs; " \ 157 "nand read ${loadaddr} 280000 400000; " \ 158 "bootm ${loadaddr}\0" \ 159 "netboot=echo Booting from network ...; " \ 160 "dhcp ${loadaddr}; " \ 161 "run netargs; " \ 162 "bootm ${loadaddr}\0" \ 163 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 164 "if run loadbootscript; then " \ 165 "run bootscript; " \ 166 "else " \ 167 "if run loaduimage; then " \ 168 "run mmcboot; " \ 169 "else run nandboot; " \ 170 "fi; " \ 171 "fi; " \ 172 "else run nandboot; fi\0" 173 174 #define CONFIG_BOOTCOMMAND "run autoboot" 175 176 /* Boot Argument Buffer Size */ 177 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 178 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 179 0x01000000) /* 16MB */ 180 181 /* NAND and environment organization */ 182 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 183 184 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 185 186 /* SRAM config */ 187 #define CONFIG_SYS_SRAM_START 0x40200000 188 #define CONFIG_SYS_SRAM_SIZE 0x10000 189 190 /* Defines for SPL */ 191 192 #undef CONFIG_SPL_TEXT_BASE 193 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 194 195 /* NAND boot config */ 196 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 197 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 198 #define CONFIG_SYS_NAND_PAGE_COUNT 64 199 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 200 #define CONFIG_SYS_NAND_OOBSIZE 64 201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 202 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 203 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 204 10, 11, 12, 13} 205 206 #define CONFIG_SYS_NAND_ECCSIZE 512 207 #define CONFIG_SYS_NAND_ECCBYTES 3 208 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 209 210 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 211 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 212 213 /* SPL OS boot options */ 214 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 215 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 216 0x400000) 217 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 218 219 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 220 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 221 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 222 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 223 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 224 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 225 226 #undef CONFIG_SYS_SPL_ARGS_ADDR 227 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 228 229 #endif /* __CONFIG_H */ 230