1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 37 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 38 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 39 #define CONFIG_OMAP_GPIO 40 41 /* 42 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 43 * 64 bytes before this address should be set aside for u-boot.img's 44 * header. That is 0x800FFFC0--0x80100000 should not be used for any 45 * other needs. 46 */ 47 #define CONFIG_SYS_TEXT_BASE 0x80100000 48 49 #define CONFIG_SDRC /* The chip has SDRC controller */ 50 51 #include <asm/arch/cpu.h> /* get chip and board defs */ 52 #include <asm/arch/omap3.h> 53 54 /* Display CPU and Board information */ 55 #define CONFIG_DISPLAY_CPUINFO 1 56 #define CONFIG_DISPLAY_BOARDINFO 1 57 58 /* Clock Defines */ 59 #define V_OSCK 26000000 /* Clock output from T2 */ 60 #define V_SCLK (V_OSCK >> 1) 61 62 #define CONFIG_MISC_INIT_R 63 64 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 65 #define CONFIG_SETUP_MEMORY_TAGS 1 66 #define CONFIG_INITRD_TAG 1 67 #define CONFIG_REVISION_TAG 1 68 69 #define CONFIG_OF_LIBFDT 1 70 71 /* Size of malloc() pool */ 72 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 73 /* Sector */ 74 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 75 76 /* Hardware drivers */ 77 /* DM9000 */ 78 #define CONFIG_NET_RETRY_COUNT 20 79 #define CONFIG_DRIVER_DM9000 1 80 #define CONFIG_DM9000_BASE 0x2c000000 81 #define DM9000_IO CONFIG_DM9000_BASE 82 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 83 #define CONFIG_DM9000_USE_16BIT 1 84 #define CONFIG_DM9000_NO_SROM 1 85 #undef CONFIG_DM9000_DEBUG 86 87 /* NS16550 Configuration */ 88 #define CONFIG_SYS_NS16550 89 #define CONFIG_SYS_NS16550_SERIAL 90 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 91 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 92 93 /* select serial console configuration */ 94 #define CONFIG_CONS_INDEX 3 95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 96 #define CONFIG_SERIAL3 3 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 101 /* MMC */ 102 #define CONFIG_GENERIC_MMC 1 103 #define CONFIG_MMC 1 104 #define CONFIG_OMAP_HSMMC 1 105 #define CONFIG_DOS_PARTITION 1 106 107 /* I2C */ 108 #define CONFIG_HARD_I2C 1 109 #define CONFIG_SYS_I2C_SPEED 100000 110 #define CONFIG_SYS_I2C_SLAVE 1 111 #define CONFIG_SYS_I2C_BUS 0 112 #define CONFIG_SYS_I2C_BUS_SELECT 1 113 #define CONFIG_DRIVER_OMAP34XX_I2C 1 114 115 /* TWL4030 */ 116 #define CONFIG_TWL4030_POWER 1 117 #define CONFIG_TWL4030_LED 1 118 119 /* Board NAND Info */ 120 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 121 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 122 #define MTDIDS_DEFAULT "nand0=nand" 123 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 124 "512k(x-loader)," \ 125 "1920k(u-boot)," \ 126 "128k(u-boot-env)," \ 127 "4m(kernel)," \ 128 "-(fs)" 129 130 #define CONFIG_NAND_OMAP_GPMC 131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 132 /* to access nand */ 133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 134 /* to access nand at */ 135 /* CS0 */ 136 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 137 138 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 139 /* devices */ 140 #define CONFIG_JFFS2_NAND 141 /* nand device jffs2 lives on */ 142 #define CONFIG_JFFS2_DEV "nand0" 143 /* start of jffs2 partition */ 144 #define CONFIG_JFFS2_PART_OFFSET 0x680000 145 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 146 /* partition */ 147 148 /* commands to include */ 149 #include <config_cmd_default.h> 150 151 #define CONFIG_CMD_DHCP /* DHCP support */ 152 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 153 #define CONFIG_CMD_FAT /* FAT support */ 154 #define CONFIG_CMD_I2C /* I2C serial bus support */ 155 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 156 #define CONFIG_CMD_MMC /* MMC support */ 157 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 158 #define CONFIG_CMD_NAND /* NAND support */ 159 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 160 161 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 162 #undef CONFIG_CMD_IMI /* iminfo */ 163 164 /* BOOTP/DHCP options */ 165 #define CONFIG_BOOTP_SUBNETMASK 166 #define CONFIG_BOOTP_GATEWAY 167 #define CONFIG_BOOTP_HOSTNAME 168 #define CONFIG_BOOTP_NISDOMAIN 169 #define CONFIG_BOOTP_BOOTPATH 170 #define CONFIG_BOOTP_BOOTFILESIZE 171 #define CONFIG_BOOTP_DNS 172 #define CONFIG_BOOTP_DNS2 173 #define CONFIG_BOOTP_SEND_HOSTNAME 174 #define CONFIG_BOOTP_NTPSERVER 175 #define CONFIG_BOOTP_TIMEOFFSET 176 #undef CONFIG_BOOTP_VENDOREX 177 178 /* Environment information */ 179 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 180 181 #define CONFIG_BOOTDELAY 3 182 183 #define CONFIG_EXTRA_ENV_SETTINGS \ 184 "loadaddr=0x82000000\0" \ 185 "console=ttyO2,115200n8\0" \ 186 "mmcdev=0\0" \ 187 "vram=12M\0" \ 188 "dvimode=1024x768MR-16@60\0" \ 189 "defaultdisplay=dvi\0" \ 190 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 191 "kernelopts=rw\0" \ 192 "commonargs=" \ 193 "setenv bootargs console=${console} " \ 194 "vram=${vram} " \ 195 "omapfb.mode=dvi:${dvimode} " \ 196 "omapdss.def_disp=${defaultdisplay}\0" \ 197 "mmcargs=" \ 198 "run commonargs; " \ 199 "setenv bootargs ${bootargs} " \ 200 "root=/dev/mmcblk0p2 " \ 201 "rootwait " \ 202 "${kernelopts}\0" \ 203 "nandargs=" \ 204 "run commonargs; " \ 205 "setenv bootargs ${bootargs} " \ 206 "omapfb.mode=dvi:${dvimode} " \ 207 "omapdss.def_disp=${defaultdisplay} " \ 208 "root=/dev/mtdblock4 " \ 209 "rootfstype=jffs2 " \ 210 "${kernelopts}\0" \ 211 "netargs=" \ 212 "run commonargs; " \ 213 "setenv bootargs ${bootargs} " \ 214 "root=/dev/nfs " \ 215 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 216 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 217 "${kernelopts} " \ 218 "dnsip1=${dnsip} " \ 219 "dnsip2=${dnsip2}\0" \ 220 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 221 "bootscript=echo Running bootscript from mmc ...; " \ 222 "source ${loadaddr}\0" \ 223 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 224 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 225 "mmcboot=echo Booting from mmc ...; " \ 226 "run mmcargs; " \ 227 "bootm ${loadaddr}\0" \ 228 "nandboot=echo Booting from nand ...; " \ 229 "run nandargs; " \ 230 "nand read ${loadaddr} 280000 400000; " \ 231 "bootm ${loadaddr}\0" \ 232 "netboot=echo Booting from network ...; " \ 233 "dhcp ${loadaddr}; " \ 234 "run netargs; " \ 235 "bootm ${loadaddr}\0" \ 236 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 237 "if run loadbootscript; then " \ 238 "run bootscript; " \ 239 "else " \ 240 "if run loaduimage; then " \ 241 "run mmcboot; " \ 242 "else run nandboot; " \ 243 "fi; " \ 244 "fi; " \ 245 "else run nandboot; fi\0" 246 247 248 #define CONFIG_BOOTCOMMAND "run autoboot" 249 250 /* Miscellaneous configurable options */ 251 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 252 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 253 #define CONFIG_AUTO_COMPLETE 1 254 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 255 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 256 /* Print Buffer Size */ 257 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 258 sizeof(CONFIG_SYS_PROMPT) + 16) 259 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 260 261 /* Boot Argument Buffer Size */ 262 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 263 264 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 265 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 266 0x01000000) /* 16MB */ 267 268 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 269 270 /* 271 * OMAP3 has 12 GP timers, they can be driven by the system clock 272 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 273 * This rate is divided by a local divisor. 274 */ 275 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 276 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 277 #define CONFIG_SYS_HZ 1000 278 279 /* Physical Memory Map */ 280 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 281 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 282 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 283 284 /* NAND and environment organization */ 285 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 286 287 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 288 289 #define CONFIG_ENV_IS_IN_NAND 1 290 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 291 292 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 293 294 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 295 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 296 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 297 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 298 CONFIG_SYS_INIT_RAM_SIZE - \ 299 GENERATED_GBL_DATA_SIZE) 300 301 /* SRAM config */ 302 #define CONFIG_SYS_SRAM_START 0x40200000 303 #define CONFIG_SYS_SRAM_SIZE 0x10000 304 305 /* Defines for SPL */ 306 #define CONFIG_SPL 307 #define CONFIG_SPL_FRAMEWORK 308 #define CONFIG_SPL_NAND_SIMPLE 309 310 #define CONFIG_SPL_LIBCOMMON_SUPPORT 311 #define CONFIG_SPL_LIBDISK_SUPPORT 312 #define CONFIG_SPL_BOARD_INIT 313 #define CONFIG_SPL_I2C_SUPPORT 314 #define CONFIG_SPL_LIBGENERIC_SUPPORT 315 #define CONFIG_SPL_SERIAL_SUPPORT 316 #define CONFIG_SPL_GPIO_SUPPORT 317 #define CONFIG_SPL_POWER_SUPPORT 318 #define CONFIG_SPL_NAND_SUPPORT 319 #define CONFIG_SPL_NAND_BASE 320 #define CONFIG_SPL_NAND_DRIVERS 321 #define CONFIG_SPL_NAND_ECC 322 #define CONFIG_SPL_MMC_SUPPORT 323 #define CONFIG_SPL_FAT_SUPPORT 324 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 325 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 326 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 327 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 328 329 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 330 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 331 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 332 333 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 334 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 335 336 /* NAND boot config */ 337 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 338 #define CONFIG_SYS_NAND_PAGE_COUNT 64 339 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 340 #define CONFIG_SYS_NAND_OOBSIZE 64 341 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 342 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 343 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 344 10, 11, 12, 13} 345 346 #define CONFIG_SYS_NAND_ECCSIZE 512 347 #define CONFIG_SYS_NAND_ECCBYTES 3 348 349 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 350 351 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 352 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 353 354 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 355 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 356 357 /* SPL OS boot options */ 358 #define CONFIG_SPL_OS_BOOT 359 #define CONFIG_SPL_OS_BOOT_KEY 26 360 361 #define CONFIG_CMD_SPL 362 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 363 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 364 0x400000) 365 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 366 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 367 368 #endif /* __CONFIG_H */ 369