1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* High Level Configuration Options */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 21 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 22 #define CONFIG_OMAP_GPIO 23 #define CONFIG_OMAP_COMMON 24 25 /* 26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27 * 64 bytes before this address should be set aside for u-boot.img's 28 * header. That is 0x800FFFC0--0x80100000 should not be used for any 29 * other needs. 30 */ 31 #define CONFIG_SYS_TEXT_BASE 0x80100000 32 33 #define CONFIG_SDRC /* The chip has SDRC controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap3.h> 37 38 /* Display CPU and Board information */ 39 #define CONFIG_DISPLAY_CPUINFO 1 40 #define CONFIG_DISPLAY_BOARDINFO 1 41 42 /* Clock Defines */ 43 #define V_OSCK 26000000 /* Clock output from T2 */ 44 #define V_SCLK (V_OSCK >> 1) 45 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 49 #define CONFIG_SETUP_MEMORY_TAGS 1 50 #define CONFIG_INITRD_TAG 1 51 #define CONFIG_REVISION_TAG 1 52 53 #define CONFIG_OF_LIBFDT 1 54 55 /* Size of malloc() pool */ 56 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 57 /* Sector */ 58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 59 60 /* Hardware drivers */ 61 /* DM9000 */ 62 #define CONFIG_NET_RETRY_COUNT 20 63 #define CONFIG_DRIVER_DM9000 1 64 #define CONFIG_DM9000_BASE 0x2c000000 65 #define DM9000_IO CONFIG_DM9000_BASE 66 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 67 #define CONFIG_DM9000_USE_16BIT 1 68 #define CONFIG_DM9000_NO_SROM 1 69 #undef CONFIG_DM9000_DEBUG 70 71 /* NS16550 Configuration */ 72 #define CONFIG_SYS_NS16550 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 76 77 /* select serial console configuration */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 #define CONFIG_SERIAL3 3 81 #define CONFIG_BAUDRATE 115200 82 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 83 115200} 84 85 /* MMC */ 86 #define CONFIG_GENERIC_MMC 1 87 #define CONFIG_MMC 1 88 #define CONFIG_OMAP_HSMMC 1 89 #define CONFIG_DOS_PARTITION 1 90 91 /* I2C */ 92 #define CONFIG_SYS_I2C 93 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 94 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 95 #define CONFIG_SYS_I2C_OMAP34XX 96 97 /* TWL4030 */ 98 #define CONFIG_TWL4030_POWER 1 99 #define CONFIG_TWL4030_LED 1 100 101 /* Board NAND Info */ 102 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 103 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 104 #define MTDIDS_DEFAULT "nand0=nand" 105 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 106 "512k(x-loader)," \ 107 "1920k(u-boot)," \ 108 "128k(u-boot-env)," \ 109 "4m(kernel)," \ 110 "-(fs)" 111 112 #define CONFIG_NAND_OMAP_GPMC 113 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 114 /* to access nand */ 115 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 116 /* to access nand at */ 117 /* CS0 */ 118 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 119 /* devices */ 120 #define CONFIG_JFFS2_NAND 121 /* nand device jffs2 lives on */ 122 #define CONFIG_JFFS2_DEV "nand0" 123 /* start of jffs2 partition */ 124 #define CONFIG_JFFS2_PART_OFFSET 0x680000 125 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 126 /* partition */ 127 128 /* commands to include */ 129 #include <config_cmd_default.h> 130 131 #define CONFIG_CMD_DHCP /* DHCP support */ 132 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 133 #define CONFIG_CMD_FAT /* FAT support */ 134 #define CONFIG_CMD_I2C /* I2C serial bus support */ 135 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 136 #define CONFIG_CMD_MMC /* MMC support */ 137 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 138 #define CONFIG_CMD_NAND /* NAND support */ 139 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 140 141 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 142 #undef CONFIG_CMD_IMI /* iminfo */ 143 144 /* BOOTP/DHCP options */ 145 #define CONFIG_BOOTP_SUBNETMASK 146 #define CONFIG_BOOTP_GATEWAY 147 #define CONFIG_BOOTP_HOSTNAME 148 #define CONFIG_BOOTP_NISDOMAIN 149 #define CONFIG_BOOTP_BOOTPATH 150 #define CONFIG_BOOTP_BOOTFILESIZE 151 #define CONFIG_BOOTP_DNS 152 #define CONFIG_BOOTP_DNS2 153 #define CONFIG_BOOTP_SEND_HOSTNAME 154 #define CONFIG_BOOTP_NTPSERVER 155 #define CONFIG_BOOTP_TIMEOFFSET 156 #undef CONFIG_BOOTP_VENDOREX 157 158 /* Environment information */ 159 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 160 161 #define CONFIG_BOOTDELAY 3 162 163 #define CONFIG_EXTRA_ENV_SETTINGS \ 164 "loadaddr=0x82000000\0" \ 165 "console=ttyO2,115200n8\0" \ 166 "mmcdev=0\0" \ 167 "vram=12M\0" \ 168 "dvimode=1024x768MR-16@60\0" \ 169 "defaultdisplay=dvi\0" \ 170 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 171 "kernelopts=rw\0" \ 172 "commonargs=" \ 173 "setenv bootargs console=${console} " \ 174 "vram=${vram} " \ 175 "omapfb.mode=dvi:${dvimode} " \ 176 "omapdss.def_disp=${defaultdisplay}\0" \ 177 "mmcargs=" \ 178 "run commonargs; " \ 179 "setenv bootargs ${bootargs} " \ 180 "root=/dev/mmcblk0p2 " \ 181 "rootwait " \ 182 "${kernelopts}\0" \ 183 "nandargs=" \ 184 "run commonargs; " \ 185 "setenv bootargs ${bootargs} " \ 186 "omapfb.mode=dvi:${dvimode} " \ 187 "omapdss.def_disp=${defaultdisplay} " \ 188 "root=/dev/mtdblock4 " \ 189 "rootfstype=jffs2 " \ 190 "${kernelopts}\0" \ 191 "netargs=" \ 192 "run commonargs; " \ 193 "setenv bootargs ${bootargs} " \ 194 "root=/dev/nfs " \ 195 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 196 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 197 "${kernelopts} " \ 198 "dnsip1=${dnsip} " \ 199 "dnsip2=${dnsip2}\0" \ 200 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 201 "bootscript=echo Running bootscript from mmc ...; " \ 202 "source ${loadaddr}\0" \ 203 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 204 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 205 "mmcboot=echo Booting from mmc ...; " \ 206 "run mmcargs; " \ 207 "bootm ${loadaddr}\0" \ 208 "nandboot=echo Booting from nand ...; " \ 209 "run nandargs; " \ 210 "nand read ${loadaddr} 280000 400000; " \ 211 "bootm ${loadaddr}\0" \ 212 "netboot=echo Booting from network ...; " \ 213 "dhcp ${loadaddr}; " \ 214 "run netargs; " \ 215 "bootm ${loadaddr}\0" \ 216 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 217 "if run loadbootscript; then " \ 218 "run bootscript; " \ 219 "else " \ 220 "if run loaduimage; then " \ 221 "run mmcboot; " \ 222 "else run nandboot; " \ 223 "fi; " \ 224 "fi; " \ 225 "else run nandboot; fi\0" 226 227 228 #define CONFIG_BOOTCOMMAND "run autoboot" 229 230 /* Miscellaneous configurable options */ 231 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 232 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 233 #define CONFIG_AUTO_COMPLETE 1 234 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 235 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 236 /* Print Buffer Size */ 237 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 238 sizeof(CONFIG_SYS_PROMPT) + 16) 239 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 240 241 /* Boot Argument Buffer Size */ 242 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 243 244 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 245 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 246 0x01000000) /* 16MB */ 247 248 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 249 250 /* 251 * OMAP3 has 12 GP timers, they can be driven by the system clock 252 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 253 * This rate is divided by a local divisor. 254 */ 255 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 256 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 257 258 /* Physical Memory Map */ 259 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 260 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 261 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 262 263 /* NAND and environment organization */ 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 265 266 #define CONFIG_ENV_IS_IN_NAND 1 267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 268 269 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 270 271 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 272 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 273 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 274 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 275 CONFIG_SYS_INIT_RAM_SIZE - \ 276 GENERATED_GBL_DATA_SIZE) 277 278 /* SRAM config */ 279 #define CONFIG_SYS_SRAM_START 0x40200000 280 #define CONFIG_SYS_SRAM_SIZE 0x10000 281 282 /* Defines for SPL */ 283 #define CONFIG_SPL_FRAMEWORK 284 #define CONFIG_SPL_NAND_SIMPLE 285 286 #define CONFIG_SPL_LIBCOMMON_SUPPORT 287 #define CONFIG_SPL_LIBDISK_SUPPORT 288 #define CONFIG_SPL_BOARD_INIT 289 #define CONFIG_SPL_I2C_SUPPORT 290 #define CONFIG_SPL_LIBGENERIC_SUPPORT 291 #define CONFIG_SPL_SERIAL_SUPPORT 292 #define CONFIG_SPL_GPIO_SUPPORT 293 #define CONFIG_SPL_POWER_SUPPORT 294 #define CONFIG_SPL_NAND_SUPPORT 295 #define CONFIG_SPL_NAND_BASE 296 #define CONFIG_SPL_NAND_DRIVERS 297 #define CONFIG_SPL_NAND_ECC 298 #define CONFIG_SPL_MMC_SUPPORT 299 #define CONFIG_SPL_FAT_SUPPORT 300 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 301 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 302 #define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 303 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 304 305 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 306 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 307 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 308 309 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 310 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 311 312 /* NAND boot config */ 313 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 314 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 315 #define CONFIG_SYS_NAND_PAGE_COUNT 64 316 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 317 #define CONFIG_SYS_NAND_OOBSIZE 64 318 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 319 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 320 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 321 10, 11, 12, 13} 322 323 #define CONFIG_SYS_NAND_ECCSIZE 512 324 #define CONFIG_SYS_NAND_ECCBYTES 3 325 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 326 327 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 328 329 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 330 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 331 332 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 333 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 334 335 /* SPL OS boot options */ 336 #define CONFIG_SPL_OS_BOOT 337 338 #define CONFIG_CMD_SPL 339 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 340 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 341 0x400000) 342 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 343 344 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 345 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 346 347 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 348 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 349 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 350 351 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 352 353 #endif /* __CONFIG_H */ 354