1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* High Level Configuration Options */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 21 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 22 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 23 #define CONFIG_OMAP_GPIO 24 #define CONFIG_OMAP_COMMON 25 26 /* 27 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 28 * 64 bytes before this address should be set aside for u-boot.img's 29 * header. That is 0x800FFFC0--0x80100000 should not be used for any 30 * other needs. 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0x80100000 33 34 #define CONFIG_SDRC /* The chip has SDRC controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap3.h> 38 39 /* Display CPU and Board information */ 40 #define CONFIG_DISPLAY_CPUINFO 1 41 #define CONFIG_DISPLAY_BOARDINFO 1 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #define CONFIG_MISC_INIT_R 48 49 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 50 #define CONFIG_SETUP_MEMORY_TAGS 1 51 #define CONFIG_INITRD_TAG 1 52 #define CONFIG_REVISION_TAG 1 53 54 #define CONFIG_OF_LIBFDT 1 55 56 /* Size of malloc() pool */ 57 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 58 /* Sector */ 59 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 60 61 /* Hardware drivers */ 62 /* DM9000 */ 63 #define CONFIG_NET_RETRY_COUNT 20 64 #define CONFIG_DRIVER_DM9000 1 65 #define CONFIG_DM9000_BASE 0x2c000000 66 #define DM9000_IO CONFIG_DM9000_BASE 67 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 68 #define CONFIG_DM9000_USE_16BIT 1 69 #define CONFIG_DM9000_NO_SROM 1 70 #undef CONFIG_DM9000_DEBUG 71 72 /* NS16550 Configuration */ 73 #define CONFIG_SYS_NS16550 74 #define CONFIG_SYS_NS16550_SERIAL 75 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 76 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 77 78 /* select serial console configuration */ 79 #define CONFIG_CONS_INDEX 3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 81 #define CONFIG_SERIAL3 3 82 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 84 115200} 85 86 /* MMC */ 87 #define CONFIG_GENERIC_MMC 1 88 #define CONFIG_MMC 1 89 #define CONFIG_OMAP_HSMMC 1 90 #define CONFIG_DOS_PARTITION 1 91 92 /* I2C */ 93 #define CONFIG_SYS_I2C 94 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 95 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 96 #define CONFIG_SYS_I2C_OMAP34XX 97 98 /* TWL4030 */ 99 #define CONFIG_TWL4030_POWER 1 100 #define CONFIG_TWL4030_LED 1 101 102 /* Board NAND Info */ 103 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 104 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 105 #define MTDIDS_DEFAULT "nand0=nand" 106 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 107 "512k(x-loader)," \ 108 "1920k(u-boot)," \ 109 "128k(u-boot-env)," \ 110 "4m(kernel)," \ 111 "-(fs)" 112 113 #define CONFIG_NAND_OMAP_GPMC 114 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 115 /* to access nand */ 116 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 117 /* to access nand at */ 118 /* CS0 */ 119 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 120 121 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 122 /* devices */ 123 #define CONFIG_JFFS2_NAND 124 /* nand device jffs2 lives on */ 125 #define CONFIG_JFFS2_DEV "nand0" 126 /* start of jffs2 partition */ 127 #define CONFIG_JFFS2_PART_OFFSET 0x680000 128 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 129 /* partition */ 130 131 /* commands to include */ 132 #include <config_cmd_default.h> 133 134 #define CONFIG_CMD_DHCP /* DHCP support */ 135 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 136 #define CONFIG_CMD_FAT /* FAT support */ 137 #define CONFIG_CMD_I2C /* I2C serial bus support */ 138 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 139 #define CONFIG_CMD_MMC /* MMC support */ 140 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 141 #define CONFIG_CMD_NAND /* NAND support */ 142 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 143 144 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 145 #undef CONFIG_CMD_IMI /* iminfo */ 146 147 /* BOOTP/DHCP options */ 148 #define CONFIG_BOOTP_SUBNETMASK 149 #define CONFIG_BOOTP_GATEWAY 150 #define CONFIG_BOOTP_HOSTNAME 151 #define CONFIG_BOOTP_NISDOMAIN 152 #define CONFIG_BOOTP_BOOTPATH 153 #define CONFIG_BOOTP_BOOTFILESIZE 154 #define CONFIG_BOOTP_DNS 155 #define CONFIG_BOOTP_DNS2 156 #define CONFIG_BOOTP_SEND_HOSTNAME 157 #define CONFIG_BOOTP_NTPSERVER 158 #define CONFIG_BOOTP_TIMEOFFSET 159 #undef CONFIG_BOOTP_VENDOREX 160 161 /* Environment information */ 162 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 163 164 #define CONFIG_BOOTDELAY 3 165 166 #define CONFIG_EXTRA_ENV_SETTINGS \ 167 "loadaddr=0x82000000\0" \ 168 "console=ttyO2,115200n8\0" \ 169 "mmcdev=0\0" \ 170 "vram=12M\0" \ 171 "dvimode=1024x768MR-16@60\0" \ 172 "defaultdisplay=dvi\0" \ 173 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 174 "kernelopts=rw\0" \ 175 "commonargs=" \ 176 "setenv bootargs console=${console} " \ 177 "vram=${vram} " \ 178 "omapfb.mode=dvi:${dvimode} " \ 179 "omapdss.def_disp=${defaultdisplay}\0" \ 180 "mmcargs=" \ 181 "run commonargs; " \ 182 "setenv bootargs ${bootargs} " \ 183 "root=/dev/mmcblk0p2 " \ 184 "rootwait " \ 185 "${kernelopts}\0" \ 186 "nandargs=" \ 187 "run commonargs; " \ 188 "setenv bootargs ${bootargs} " \ 189 "omapfb.mode=dvi:${dvimode} " \ 190 "omapdss.def_disp=${defaultdisplay} " \ 191 "root=/dev/mtdblock4 " \ 192 "rootfstype=jffs2 " \ 193 "${kernelopts}\0" \ 194 "netargs=" \ 195 "run commonargs; " \ 196 "setenv bootargs ${bootargs} " \ 197 "root=/dev/nfs " \ 198 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 199 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 200 "${kernelopts} " \ 201 "dnsip1=${dnsip} " \ 202 "dnsip2=${dnsip2}\0" \ 203 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 204 "bootscript=echo Running bootscript from mmc ...; " \ 205 "source ${loadaddr}\0" \ 206 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 207 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 208 "mmcboot=echo Booting from mmc ...; " \ 209 "run mmcargs; " \ 210 "bootm ${loadaddr}\0" \ 211 "nandboot=echo Booting from nand ...; " \ 212 "run nandargs; " \ 213 "nand read ${loadaddr} 280000 400000; " \ 214 "bootm ${loadaddr}\0" \ 215 "netboot=echo Booting from network ...; " \ 216 "dhcp ${loadaddr}; " \ 217 "run netargs; " \ 218 "bootm ${loadaddr}\0" \ 219 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 220 "if run loadbootscript; then " \ 221 "run bootscript; " \ 222 "else " \ 223 "if run loaduimage; then " \ 224 "run mmcboot; " \ 225 "else run nandboot; " \ 226 "fi; " \ 227 "fi; " \ 228 "else run nandboot; fi\0" 229 230 231 #define CONFIG_BOOTCOMMAND "run autoboot" 232 233 /* Miscellaneous configurable options */ 234 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 235 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 236 #define CONFIG_AUTO_COMPLETE 1 237 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " 238 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 239 /* Print Buffer Size */ 240 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 241 sizeof(CONFIG_SYS_PROMPT) + 16) 242 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ 243 244 /* Boot Argument Buffer Size */ 245 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 246 247 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 248 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 249 0x01000000) /* 16MB */ 250 251 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 252 253 /* 254 * OMAP3 has 12 GP timers, they can be driven by the system clock 255 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 256 * This rate is divided by a local divisor. 257 */ 258 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 259 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 260 261 /* Physical Memory Map */ 262 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 263 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 264 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 265 266 /* NAND and environment organization */ 267 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 268 269 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 270 271 #define CONFIG_ENV_IS_IN_NAND 1 272 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 273 274 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 275 276 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 277 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 278 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 279 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 280 CONFIG_SYS_INIT_RAM_SIZE - \ 281 GENERATED_GBL_DATA_SIZE) 282 283 /* SRAM config */ 284 #define CONFIG_SYS_SRAM_START 0x40200000 285 #define CONFIG_SYS_SRAM_SIZE 0x10000 286 287 /* Defines for SPL */ 288 #define CONFIG_SPL 289 #define CONFIG_SPL_FRAMEWORK 290 #define CONFIG_SPL_NAND_SIMPLE 291 292 #define CONFIG_SPL_LIBCOMMON_SUPPORT 293 #define CONFIG_SPL_LIBDISK_SUPPORT 294 #define CONFIG_SPL_BOARD_INIT 295 #define CONFIG_SPL_I2C_SUPPORT 296 #define CONFIG_SPL_LIBGENERIC_SUPPORT 297 #define CONFIG_SPL_SERIAL_SUPPORT 298 #define CONFIG_SPL_GPIO_SUPPORT 299 #define CONFIG_SPL_POWER_SUPPORT 300 #define CONFIG_SPL_NAND_SUPPORT 301 #define CONFIG_SPL_NAND_BASE 302 #define CONFIG_SPL_NAND_DRIVERS 303 #define CONFIG_SPL_NAND_ECC 304 #define CONFIG_SPL_MMC_SUPPORT 305 #define CONFIG_SPL_FAT_SUPPORT 306 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 307 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 308 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 309 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 310 311 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 312 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 313 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 314 315 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 316 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 317 318 /* NAND boot config */ 319 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 320 #define CONFIG_SYS_NAND_PAGE_COUNT 64 321 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 322 #define CONFIG_SYS_NAND_OOBSIZE 64 323 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 324 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 325 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 326 10, 11, 12, 13} 327 328 #define CONFIG_SYS_NAND_ECCSIZE 512 329 #define CONFIG_SYS_NAND_ECCBYTES 3 330 331 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 332 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 334 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 335 336 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 337 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 338 339 /* SPL OS boot options */ 340 #define CONFIG_SPL_OS_BOOT 341 342 #define CONFIG_CMD_SPL 343 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 344 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 345 0x400000) 346 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 347 348 #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" 349 #define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" 350 351 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 352 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 353 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 354 355 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 356 357 #endif /* __CONFIG_H */ 358