1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Embest/Timll DevKit3250 board configuration file 4 * 5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 6 */ 7 8 #ifndef __CONFIG_DEVKIT3250_H__ 9 #define __CONFIG_DEVKIT3250_H__ 10 11 /* SoC and board defines */ 12 #include <linux/sizes.h> 13 #include <asm/arch/cpu.h> 14 15 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 16 17 #define CONFIG_SYS_ICACHE_OFF 18 #define CONFIG_SYS_DCACHE_OFF 19 #if !defined(CONFIG_SPL_BUILD) 20 #define CONFIG_SKIP_LOWLEVEL_INIT 21 #endif 22 23 /* 24 * Memory configurations 25 */ 26 #define CONFIG_NR_DRAM_BANKS 1 27 #define CONFIG_SYS_MALLOC_LEN SZ_1M 28 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 29 #define CONFIG_SYS_SDRAM_SIZE SZ_64M 30 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 32 33 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 34 35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 36 - GENERATED_GBL_DATA_SIZE) 37 38 /* 39 * Serial Driver 40 */ 41 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ 42 43 /* 44 * DMA 45 */ 46 #if !defined(CONFIG_SPL_BUILD) 47 #define CONFIG_DMA_LPC32XX 48 #endif 49 50 /* 51 * I2C 52 */ 53 #define CONFIG_SYS_I2C 54 #define CONFIG_SYS_I2C_LPC32XX 55 #define CONFIG_SYS_I2C_SPEED 100000 56 57 /* 58 * GPIO 59 */ 60 #define CONFIG_LPC32XX_GPIO 61 62 /* 63 * SSP/SPI 64 */ 65 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 66 67 /* 68 * Ethernet 69 */ 70 #define CONFIG_RMII 71 #define CONFIG_PHY_SMSC 72 #define CONFIG_LPC32XX_ETH 73 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 75 /* 76 * NOR Flash 77 */ 78 #define CONFIG_SYS_MAX_FLASH_BANKS 1 79 #define CONFIG_SYS_MAX_FLASH_SECT 71 80 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE 81 #define CONFIG_SYS_FLASH_SIZE SZ_4M 82 #define CONFIG_SYS_FLASH_CFI 83 84 /* 85 * NAND controller 86 */ 87 #define CONFIG_NAND_LPC32XX_SLC 88 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE 89 #define CONFIG_SYS_MAX_NAND_DEVICE 1 90 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 91 92 /* 93 * NAND chip timings 94 */ 95 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 96 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 97 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 98 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 99 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 100 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 101 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 102 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 103 104 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 105 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 106 #define CONFIG_SYS_NAND_USE_FLASH_BBT 107 108 /* 109 * USB 110 */ 111 #define CONFIG_USB_OHCI_LPC32XX 112 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 113 114 /* 115 * U-Boot General Configurations 116 */ 117 #define CONFIG_SYS_CBSIZE 1024 118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 119 120 /* 121 * Pass open firmware flat tree 122 */ 123 124 /* 125 * Environment 126 */ 127 #define CONFIG_ENV_SIZE SZ_128K 128 #define CONFIG_ENV_OFFSET 0x000A0000 129 130 #define CONFIG_BOOTCOMMAND \ 131 "dhcp; " \ 132 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ 133 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ 134 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ 135 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ 136 "bootm ${loadaddr} - ${dtbaddr}" 137 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "autoload=no\0" \ 140 "ethaddr=00:01:90:00:C0:81\0" \ 141 "dtbaddr=0x81000000\0" \ 142 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 143 "tftpdir=vladimir/oe/devkit3250\0" \ 144 "userargs=oops=panic\0" 145 146 /* 147 * U-Boot Commands 148 */ 149 150 /* 151 * Boot Linux 152 */ 153 #define CONFIG_CMDLINE_TAG 154 #define CONFIG_SETUP_MEMORY_TAGS 155 156 #define CONFIG_BOOTFILE "uImage" 157 #define CONFIG_LOADADDR 0x80008000 158 159 /* 160 * SPL specific defines 161 */ 162 /* SPL will be executed at offset 0 */ 163 #define CONFIG_SPL_TEXT_BASE 0x00000000 164 165 /* SPL will use SRAM as stack */ 166 #define CONFIG_SPL_STACK 0x0000FFF8 167 168 /* Use the framework and generic lib */ 169 170 /* SPL will use serial */ 171 172 /* SPL loads an image from NAND */ 173 #define CONFIG_SPL_NAND_RAW_ONLY 174 #define CONFIG_SPL_NAND_DRIVERS 175 176 #define CONFIG_SPL_NAND_ECC 177 #define CONFIG_SPL_NAND_SOFTECC 178 179 #define CONFIG_SPL_MAX_SIZE 0x20000 180 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE 181 182 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 183 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 184 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 185 186 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 187 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 188 189 /* See common/spl/spl.c spl_set_header_raw_uboot() */ 190 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE 191 192 /* 193 * Include SoC specific configuration 194 */ 195 #include <asm/arch/config.h> 196 197 #endif /* __CONFIG_DEVKIT3250_H__*/ 198