1 /* 2 * Embest/Timll DevKit3250 board configuration file 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_DEVKIT3250_H__ 10 #define __CONFIG_DEVKIT3250_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 17 18 #define CONFIG_SYS_ICACHE_OFF 19 #define CONFIG_SYS_DCACHE_OFF 20 #if !defined(CONFIG_SPL_BUILD) 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #endif 23 24 /* 25 * Memory configurations 26 */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define CONFIG_SYS_MALLOC_LEN SZ_1M 29 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 30 #define CONFIG_SYS_SDRAM_SIZE SZ_64M 31 #define CONFIG_SYS_TEXT_BASE 0x83F00000 32 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 34 35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 36 37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 38 - GENERATED_GBL_DATA_SIZE) 39 40 /* 41 * Serial Driver 42 */ 43 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ 44 #define CONFIG_BAUDRATE 115200 45 46 /* 47 * DMA 48 */ 49 #if !defined(CONFIG_SPL_BUILD) 50 #define CONFIG_DMA_LPC32XX 51 #endif 52 53 /* 54 * I2C 55 */ 56 #define CONFIG_SYS_I2C 57 #define CONFIG_SYS_I2C_LPC32XX 58 #define CONFIG_SYS_I2C_SPEED 100000 59 60 /* 61 * GPIO 62 */ 63 #define CONFIG_LPC32XX_GPIO 64 65 /* 66 * SSP/SPI 67 */ 68 #define CONFIG_LPC32XX_SSP 69 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 70 71 /* 72 * Ethernet 73 */ 74 #define CONFIG_RMII 75 #define CONFIG_PHY_SMSC 76 #define CONFIG_LPC32XX_ETH 77 #define CONFIG_PHYLIB 78 #define CONFIG_PHY_ADDR 0x1F 79 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 80 81 /* 82 * NOR Flash 83 */ 84 #define CONFIG_SYS_MAX_FLASH_BANKS 1 85 #define CONFIG_SYS_MAX_FLASH_SECT 71 86 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE 87 #define CONFIG_SYS_FLASH_SIZE SZ_4M 88 #define CONFIG_SYS_FLASH_CFI 89 90 /* 91 * NAND controller 92 */ 93 #define CONFIG_NAND_LPC32XX_SLC 94 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE 95 #define CONFIG_SYS_MAX_NAND_DEVICE 1 96 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 97 98 /* 99 * NAND chip timings 100 */ 101 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 102 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 103 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 104 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 105 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 106 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 107 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 108 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 109 110 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 111 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 112 #define CONFIG_SYS_NAND_USE_FLASH_BBT 113 114 #define CONFIG_CMD_JFFS2 115 #define CONFIG_CMD_NAND 116 117 /* 118 * USB 119 */ 120 #define CONFIG_USB_OHCI_LPC32XX 121 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 122 123 /* 124 * U-Boot General Configurations 125 */ 126 #define CONFIG_SYS_LONGHELP 127 #define CONFIG_SYS_CBSIZE 1024 128 #define CONFIG_SYS_PBSIZE \ 129 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 130 #define CONFIG_SYS_MAXARGS 16 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 132 133 #define CONFIG_AUTO_COMPLETE 134 #define CONFIG_CMDLINE_EDITING 135 136 /* 137 * Pass open firmware flat tree 138 */ 139 140 /* 141 * Environment 142 */ 143 #define CONFIG_ENV_IS_IN_NAND 1 144 #define CONFIG_ENV_SIZE SZ_128K 145 #define CONFIG_ENV_OFFSET 0x000A0000 146 147 #define CONFIG_BOOTCOMMAND \ 148 "dhcp; " \ 149 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ 150 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ 151 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ 152 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ 153 "bootm ${loadaddr} - ${dtbaddr}" 154 155 #define CONFIG_EXTRA_ENV_SETTINGS \ 156 "autoload=no\0" \ 157 "ethaddr=00:01:90:00:C0:81\0" \ 158 "dtbaddr=0x81000000\0" \ 159 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 160 "tftpdir=vladimir/oe/devkit3250\0" \ 161 "userargs=oops=panic\0" 162 163 /* 164 * U-Boot Commands 165 */ 166 167 /* 168 * Boot Linux 169 */ 170 #define CONFIG_CMDLINE_TAG 171 #define CONFIG_SETUP_MEMORY_TAGS 172 173 #define CONFIG_BOOTFILE "uImage" 174 #define CONFIG_BOOTARGS "console=ttyS0,115200n8" 175 #define CONFIG_LOADADDR 0x80008000 176 177 /* 178 * SPL specific defines 179 */ 180 /* SPL will be executed at offset 0 */ 181 #define CONFIG_SPL_TEXT_BASE 0x00000000 182 183 /* SPL will use SRAM as stack */ 184 #define CONFIG_SPL_STACK 0x0000FFF8 185 #define CONFIG_SPL_BOARD_INIT 186 187 /* Use the framework and generic lib */ 188 #define CONFIG_SPL_FRAMEWORK 189 190 /* SPL will use serial */ 191 192 /* SPL loads an image from NAND */ 193 #define CONFIG_SPL_NAND_SIMPLE 194 #define CONFIG_SPL_NAND_RAW_ONLY 195 #define CONFIG_SPL_NAND_DRIVERS 196 197 #define CONFIG_SPL_NAND_ECC 198 #define CONFIG_SPL_NAND_SOFTECC 199 200 #define CONFIG_SPL_MAX_SIZE 0x20000 201 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE 202 203 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 204 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 205 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 206 207 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 208 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 209 210 /* See common/spl/spl.c spl_set_header_raw_uboot() */ 211 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE 212 213 /* 214 * Include SoC specific configuration 215 */ 216 #include <asm/arch/config.h> 217 218 #endif /* __CONFIG_DEVKIT3250_H__*/ 219