1 /* 2 * Embest/Timll DevKit3250 board configuration file 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_DEVKIT3250_H__ 10 #define __CONFIG_DEVKIT3250_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 17 18 #define CONFIG_SYS_ICACHE_OFF 19 #define CONFIG_SYS_DCACHE_OFF 20 #if !defined(CONFIG_SPL_BUILD) 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #endif 23 24 /* 25 * Memory configurations 26 */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define CONFIG_SYS_MALLOC_LEN SZ_1M 29 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 30 #define CONFIG_SYS_SDRAM_SIZE SZ_64M 31 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 32 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 33 34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 35 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 37 - GENERATED_GBL_DATA_SIZE) 38 39 /* 40 * Serial Driver 41 */ 42 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ 43 44 /* 45 * DMA 46 */ 47 #if !defined(CONFIG_SPL_BUILD) 48 #define CONFIG_DMA_LPC32XX 49 #endif 50 51 /* 52 * I2C 53 */ 54 #define CONFIG_SYS_I2C 55 #define CONFIG_SYS_I2C_LPC32XX 56 #define CONFIG_SYS_I2C_SPEED 100000 57 58 /* 59 * GPIO 60 */ 61 #define CONFIG_LPC32XX_GPIO 62 63 /* 64 * SSP/SPI 65 */ 66 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 67 68 /* 69 * Ethernet 70 */ 71 #define CONFIG_RMII 72 #define CONFIG_PHY_SMSC 73 #define CONFIG_LPC32XX_ETH 74 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 76 /* 77 * NOR Flash 78 */ 79 #define CONFIG_SYS_MAX_FLASH_BANKS 1 80 #define CONFIG_SYS_MAX_FLASH_SECT 71 81 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE 82 #define CONFIG_SYS_FLASH_SIZE SZ_4M 83 #define CONFIG_SYS_FLASH_CFI 84 85 /* 86 * NAND controller 87 */ 88 #define CONFIG_NAND_LPC32XX_SLC 89 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE 90 #define CONFIG_SYS_MAX_NAND_DEVICE 1 91 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 92 93 /* 94 * NAND chip timings 95 */ 96 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 97 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 98 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 99 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 100 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 101 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 102 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 103 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 104 105 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 106 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 107 #define CONFIG_SYS_NAND_USE_FLASH_BBT 108 109 /* 110 * USB 111 */ 112 #define CONFIG_USB_OHCI_LPC32XX 113 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 114 115 /* 116 * U-Boot General Configurations 117 */ 118 #define CONFIG_SYS_CBSIZE 1024 119 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 120 121 /* 122 * Pass open firmware flat tree 123 */ 124 125 /* 126 * Environment 127 */ 128 #define CONFIG_ENV_SIZE SZ_128K 129 #define CONFIG_ENV_OFFSET 0x000A0000 130 131 #define CONFIG_BOOTCOMMAND \ 132 "dhcp; " \ 133 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ 134 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ 135 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ 136 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ 137 "bootm ${loadaddr} - ${dtbaddr}" 138 139 #define CONFIG_EXTRA_ENV_SETTINGS \ 140 "autoload=no\0" \ 141 "ethaddr=00:01:90:00:C0:81\0" \ 142 "dtbaddr=0x81000000\0" \ 143 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 144 "tftpdir=vladimir/oe/devkit3250\0" \ 145 "userargs=oops=panic\0" 146 147 /* 148 * U-Boot Commands 149 */ 150 151 /* 152 * Boot Linux 153 */ 154 #define CONFIG_CMDLINE_TAG 155 #define CONFIG_SETUP_MEMORY_TAGS 156 157 #define CONFIG_BOOTFILE "uImage" 158 #define CONFIG_LOADADDR 0x80008000 159 160 /* 161 * SPL specific defines 162 */ 163 /* SPL will be executed at offset 0 */ 164 #define CONFIG_SPL_TEXT_BASE 0x00000000 165 166 /* SPL will use SRAM as stack */ 167 #define CONFIG_SPL_STACK 0x0000FFF8 168 169 /* Use the framework and generic lib */ 170 171 /* SPL will use serial */ 172 173 /* SPL loads an image from NAND */ 174 #define CONFIG_SPL_NAND_RAW_ONLY 175 #define CONFIG_SPL_NAND_DRIVERS 176 177 #define CONFIG_SPL_NAND_ECC 178 #define CONFIG_SPL_NAND_SOFTECC 179 180 #define CONFIG_SPL_MAX_SIZE 0x20000 181 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE 182 183 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 184 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 185 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 186 187 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 188 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 189 190 /* See common/spl/spl.c spl_set_header_raw_uboot() */ 191 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE 192 193 /* 194 * Include SoC specific configuration 195 */ 196 #include <asm/arch/config.h> 197 198 #endif /* __CONFIG_DEVKIT3250_H__*/ 199