1 /* 2 * Embest/Timll DevKit3250 board configuration file 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_DEVKIT3250_H__ 10 #define __CONFIG_DEVKIT3250_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 /* 17 * Define DevKit3250 machine type by hand until it lands in mach-types 18 */ 19 #define MACH_TYPE_DEVKIT3250 3697 20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 21 22 #define CONFIG_SYS_ICACHE_OFF 23 #define CONFIG_SYS_DCACHE_OFF 24 #if !defined(CONFIG_SPL_BUILD) 25 #define CONFIG_SKIP_LOWLEVEL_INIT 26 #endif 27 28 /* 29 * Memory configurations 30 */ 31 #define CONFIG_NR_DRAM_BANKS 1 32 #define CONFIG_SYS_MALLOC_LEN SZ_1M 33 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 34 #define CONFIG_SYS_SDRAM_SIZE SZ_64M 35 #define CONFIG_SYS_TEXT_BASE 0x83F00000 36 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 37 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 38 39 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 40 41 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 42 - GENERATED_GBL_DATA_SIZE) 43 44 /* 45 * Serial Driver 46 */ 47 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ 48 #define CONFIG_BAUDRATE 115200 49 50 /* 51 * DMA 52 */ 53 #if !defined(CONFIG_SPL_BUILD) 54 #define CONFIG_DMA_LPC32XX 55 #endif 56 57 /* 58 * I2C 59 */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_I2C_LPC32XX 62 #define CONFIG_SYS_I2C_SPEED 100000 63 64 /* 65 * GPIO 66 */ 67 #define CONFIG_LPC32XX_GPIO 68 69 /* 70 * SSP/SPI 71 */ 72 #define CONFIG_LPC32XX_SSP 73 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 74 75 /* 76 * Ethernet 77 */ 78 #define CONFIG_RMII 79 #define CONFIG_PHY_SMSC 80 #define CONFIG_LPC32XX_ETH 81 #define CONFIG_PHYLIB 82 #define CONFIG_PHY_ADDR 0x1F 83 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 84 85 /* 86 * NOR Flash 87 */ 88 #define CONFIG_SYS_MAX_FLASH_BANKS 1 89 #define CONFIG_SYS_MAX_FLASH_SECT 71 90 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE 91 #define CONFIG_SYS_FLASH_SIZE SZ_4M 92 #define CONFIG_SYS_FLASH_CFI 93 94 /* 95 * NAND controller 96 */ 97 #define CONFIG_NAND_LPC32XX_SLC 98 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE 99 #define CONFIG_SYS_MAX_NAND_DEVICE 1 100 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 101 102 /* 103 * NAND chip timings 104 */ 105 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 106 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 107 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 108 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 109 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 110 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 111 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 112 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 113 114 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 115 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 116 #define CONFIG_SYS_NAND_USE_FLASH_BBT 117 118 #define CONFIG_CMD_JFFS2 119 #define CONFIG_CMD_NAND 120 121 /* 122 * USB 123 */ 124 #define CONFIG_USB_OHCI_LPC32XX 125 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 126 127 /* 128 * U-Boot General Configurations 129 */ 130 #define CONFIG_SYS_LONGHELP 131 #define CONFIG_SYS_CBSIZE 1024 132 #define CONFIG_SYS_PBSIZE \ 133 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 134 #define CONFIG_SYS_MAXARGS 16 135 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 136 137 #define CONFIG_AUTO_COMPLETE 138 #define CONFIG_CMDLINE_EDITING 139 #define CONFIG_DOS_PARTITION 140 141 /* 142 * Pass open firmware flat tree 143 */ 144 145 /* 146 * Environment 147 */ 148 #define CONFIG_ENV_IS_IN_NAND 1 149 #define CONFIG_ENV_SIZE SZ_128K 150 #define CONFIG_ENV_OFFSET 0x000A0000 151 152 #define CONFIG_BOOTCOMMAND \ 153 "dhcp; " \ 154 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ 155 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ 156 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ 157 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ 158 "bootm ${loadaddr} - ${dtbaddr}" 159 160 #define CONFIG_EXTRA_ENV_SETTINGS \ 161 "autoload=no\0" \ 162 "ethaddr=00:01:90:00:C0:81\0" \ 163 "dtbaddr=0x81000000\0" \ 164 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 165 "tftpdir=vladimir/oe/devkit3250\0" \ 166 "userargs=oops=panic\0" 167 168 /* 169 * U-Boot Commands 170 */ 171 172 /* 173 * Boot Linux 174 */ 175 #define CONFIG_CMDLINE_TAG 176 #define CONFIG_SETUP_MEMORY_TAGS 177 178 #define CONFIG_BOOTFILE "uImage" 179 #define CONFIG_BOOTARGS "console=ttyS0,115200n8" 180 #define CONFIG_LOADADDR 0x80008000 181 182 /* 183 * SPL specific defines 184 */ 185 /* SPL will be executed at offset 0 */ 186 #define CONFIG_SPL_TEXT_BASE 0x00000000 187 188 /* SPL will use SRAM as stack */ 189 #define CONFIG_SPL_STACK 0x0000FFF8 190 #define CONFIG_SPL_BOARD_INIT 191 192 /* Use the framework and generic lib */ 193 #define CONFIG_SPL_FRAMEWORK 194 195 /* SPL will use serial */ 196 197 /* SPL loads an image from NAND */ 198 #define CONFIG_SPL_NAND_SIMPLE 199 #define CONFIG_SPL_NAND_RAW_ONLY 200 #define CONFIG_SPL_NAND_DRIVERS 201 202 #define CONFIG_SPL_NAND_ECC 203 #define CONFIG_SPL_NAND_SOFTECC 204 205 #define CONFIG_SPL_MAX_SIZE 0x20000 206 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE 207 208 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 209 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 210 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 211 212 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 213 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 214 215 /* See common/spl/spl.c spl_set_header_raw_uboot() */ 216 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE 217 218 /* 219 * Include SoC specific configuration 220 */ 221 #include <asm/arch/config.h> 222 223 #endif /* __CONFIG_DEVKIT3250_H__*/ 224