1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #ifdef CONFIG_SPL_BUILD 17 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 18 #endif 19 #define CONFIG_SYS_GENERIC_BOARD 20 #define CONFIG_DISPLAY_BOARDINFO_LATE 21 22 /* 23 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 24 * for DDR ECC byte filling in the SPL before loading the main 25 * U-Boot into it. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x00800000 28 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 29 30 /* 31 * Commands configuration 32 */ 33 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 34 #define CONFIG_CMD_DHCP 35 #define CONFIG_CMD_ENV 36 #define CONFIG_CMD_I2C 37 #define CONFIG_CMD_IDE 38 #define CONFIG_CMD_NAND 39 #define CONFIG_CMD_PCI 40 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_SF 42 #define CONFIG_CMD_SPI 43 #define CONFIG_CMD_TFTPPUT 44 #define CONFIG_CMD_TIME 45 46 /* I2C */ 47 #define CONFIG_SYS_I2C 48 #define CONFIG_SYS_I2C_MVTWSI 49 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 50 #define CONFIG_SYS_I2C_SLAVE 0x0 51 #define CONFIG_SYS_I2C_SPEED 100000 52 53 /* USB/EHCI configuration */ 54 #define CONFIG_EHCI_IS_TDI 55 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 56 57 /* SPI NOR flash default params, used by sf commands */ 58 #define CONFIG_SF_DEFAULT_SPEED 1000000 59 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 60 #define CONFIG_SPI_FLASH_STMICRO 61 62 /* Environment in SPI NOR flash */ 63 #define CONFIG_ENV_IS_IN_SPI_FLASH 64 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 65 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 66 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 67 68 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 69 #define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } 70 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII 71 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 72 #define CONFIG_RESET_PHY_R 73 74 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 75 #define CONFIG_SYS_ALT_MEMTEST 76 77 /* SATA support */ 78 #ifdef CONFIG_CMD_IDE 79 #define __io 80 #define CONFIG_IDE_PREINIT 81 #define CONFIG_MVSATA_IDE 82 83 /* Needs byte-swapping for ATA data register */ 84 #define CONFIG_IDE_SWAP_IO 85 86 #define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ 87 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ 88 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 89 90 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 91 #define CONFIG_SYS_ATA_STRIDE 4 92 93 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 94 #define CONFIG_SYS_IDE_MAXBUS 2 95 #define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS 96 97 /* ATA registers base is at SATA controller base */ 98 #define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE 99 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 100 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 101 102 #define CONFIG_DOS_PARTITION 103 #endif /* CONFIG_CMD_IDE */ 104 105 /* PCIe support */ 106 #define CONFIG_PCI 107 #define CONFIG_PCI_MVEBU 108 #define CONFIG_PCI_PNP 109 #define CONFIG_PCI_SCAN_SHOW 110 #define CONFIG_E1000 /* enable Intel E1000 support for testing */ 111 112 /* NAND */ 113 #define CONFIG_SYS_NAND_USE_FLASH_BBT 114 #define CONFIG_SYS_NAND_ONFI_DETECTION 115 116 /* 117 * mv-common.h should be defined after CMD configs since it used them 118 * to enable certain macros 119 */ 120 #include "mv-common.h" 121 122 /* 123 * Memory layout while starting into the bin_hdr via the 124 * BootROM: 125 * 126 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 127 * 0x4000.4030 bin_hdr start address 128 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 129 * 0x4007.fffc BootROM stack top 130 * 131 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 132 * L2 cache thus cannot be used. 133 */ 134 135 /* SPL */ 136 /* Defines for SPL */ 137 #define CONFIG_SPL_FRAMEWORK 138 #define CONFIG_SPL_TEXT_BASE 0x40004030 139 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 140 141 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 142 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 143 144 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 145 CONFIG_SPL_BSS_MAX_SIZE) 146 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 147 148 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 149 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 150 151 #define CONFIG_SPL_LIBCOMMON_SUPPORT 152 #define CONFIG_SPL_LIBGENERIC_SUPPORT 153 #define CONFIG_SPL_SERIAL_SUPPORT 154 #define CONFIG_SPL_I2C_SUPPORT 155 156 /* SPL related SPI defines */ 157 #define CONFIG_SPL_SPI_SUPPORT 158 #define CONFIG_SPL_SPI_FLASH_SUPPORT 159 #define CONFIG_SPL_SPI_LOAD 160 #define CONFIG_SPL_SPI_BUS 0 161 #define CONFIG_SPL_SPI_CS 0 162 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 163 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 164 165 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 166 #define CONFIG_SYS_MVEBU_DDR_AXP 167 #define CONFIG_SPD_EEPROM 0x4e 168 169 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 170