1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 17 /* 18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19 * for DDR ECC byte filling in the SPL before loading the main 20 * U-Boot into it. 21 */ 22 #define CONFIG_SYS_TEXT_BASE 0x00800000 23 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24 25 /* 26 * Commands configuration 27 */ 28 #define CONFIG_CMD_NAND 29 #define CONFIG_CMD_PCI 30 #define CONFIG_CMD_SATA 31 32 /* I2C */ 33 #define CONFIG_SYS_I2C 34 #define CONFIG_SYS_I2C_MVTWSI 35 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 36 #define CONFIG_SYS_I2C_SLAVE 0x0 37 #define CONFIG_SYS_I2C_SPEED 100000 38 39 /* USB/EHCI configuration */ 40 #define CONFIG_EHCI_IS_TDI 41 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 42 43 /* SPI NOR flash default params, used by sf commands */ 44 #define CONFIG_SF_DEFAULT_SPEED 1000000 45 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 46 47 /* Environment in SPI NOR flash */ 48 #define CONFIG_ENV_IS_IN_SPI_FLASH 49 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 50 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 51 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 52 53 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 54 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 55 56 #define CONFIG_SYS_ALT_MEMTEST 57 58 /* SATA support */ 59 #define CONFIG_SYS_SATA_MAX_DEVICE 2 60 #define CONFIG_SATA_MV 61 #define CONFIG_LIBATA 62 #define CONFIG_LBA48 63 64 /* Additional FS support/configuration */ 65 #define CONFIG_SUPPORT_VFAT 66 67 /* PCIe support */ 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_PCI_MVEBU 70 #define CONFIG_PCI_SCAN_SHOW 71 #endif 72 73 /* NAND */ 74 #define CONFIG_SYS_NAND_USE_FLASH_BBT 75 #define CONFIG_SYS_NAND_ONFI_DETECTION 76 77 /* 78 * mv-common.h should be defined after CMD configs since it used them 79 * to enable certain macros 80 */ 81 #include "mv-common.h" 82 83 /* 84 * Memory layout while starting into the bin_hdr via the 85 * BootROM: 86 * 87 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 88 * 0x4000.4030 bin_hdr start address 89 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 90 * 0x4007.fffc BootROM stack top 91 * 92 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 93 * L2 cache thus cannot be used. 94 */ 95 96 /* SPL */ 97 /* Defines for SPL */ 98 #define CONFIG_SPL_FRAMEWORK 99 #define CONFIG_SPL_TEXT_BASE 0x40004030 100 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 101 102 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 103 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 104 105 #ifdef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MALLOC_SIMPLE 107 #endif 108 109 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 110 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 111 112 /* SPL related SPI defines */ 113 #define CONFIG_SPL_SPI_LOAD 114 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 115 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 116 117 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 118 #define CONFIG_SPD_EEPROM 0x4e 119 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 120 121 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 122