1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 17 /* 18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19 * for DDR ECC byte filling in the SPL before loading the main 20 * U-Boot into it. 21 */ 22 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 23 24 /* I2C */ 25 #define CONFIG_SYS_I2C 26 #define CONFIG_SYS_I2C_MVTWSI 27 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 28 #define CONFIG_SYS_I2C_SLAVE 0x0 29 #define CONFIG_SYS_I2C_SPEED 100000 30 31 /* USB/EHCI configuration */ 32 #define CONFIG_EHCI_IS_TDI 33 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 34 35 /* SPI NOR flash default params, used by sf commands */ 36 #define CONFIG_SF_DEFAULT_SPEED 1000000 37 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 38 39 /* Environment in SPI NOR flash */ 40 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 41 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 42 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 43 44 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 45 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 46 47 #define CONFIG_SYS_ALT_MEMTEST 48 49 /* SATA support */ 50 #define CONFIG_SYS_SATA_MAX_DEVICE 2 51 #define CONFIG_LBA48 52 53 /* PCIe support */ 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_PCI_MVEBU 56 #define CONFIG_PCI_SCAN_SHOW 57 #endif 58 59 /* NAND */ 60 #define CONFIG_SYS_NAND_USE_FLASH_BBT 61 #define CONFIG_SYS_NAND_ONFI_DETECTION 62 63 /* 64 * mv-common.h should be defined after CMD configs since it used them 65 * to enable certain macros 66 */ 67 #include "mv-common.h" 68 69 /* 70 * Memory layout while starting into the bin_hdr via the 71 * BootROM: 72 * 73 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 74 * 0x4000.4030 bin_hdr start address 75 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 76 * 0x4007.fffc BootROM stack top 77 * 78 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 79 * L2 cache thus cannot be used. 80 */ 81 82 /* SPL */ 83 /* Defines for SPL */ 84 #define CONFIG_SPL_TEXT_BASE 0x40004030 85 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 86 87 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 88 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 89 90 #ifdef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MALLOC_SIMPLE 92 #endif 93 94 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 95 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 96 97 /* SPL related SPI defines */ 98 #define CONFIG_SPL_SPI_LOAD 99 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 100 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 101 102 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 103 #define CONFIG_SPD_EEPROM 0x4e 104 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 105 106 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 107