1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17 #define CONFIG_SYS_GENERIC_BOARD 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 20 /* 21 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 22 * for DDR ECC byte filling in the SPL before loading the main 23 * U-Boot into it. 24 */ 25 #define CONFIG_SYS_TEXT_BASE 0x00800000 26 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 27 28 /* 29 * Commands configuration 30 */ 31 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 32 #define CONFIG_CMD_DHCP 33 #define CONFIG_CMD_ENV 34 #define CONFIG_CMD_I2C 35 #define CONFIG_CMD_IDE 36 #define CONFIG_CMD_NAND 37 #define CONFIG_CMD_PCI 38 #define CONFIG_CMD_PING 39 #define CONFIG_CMD_SF 40 #define CONFIG_CMD_SPI 41 #define CONFIG_CMD_TFTPPUT 42 #define CONFIG_CMD_TIME 43 #define CONFIG_CMD_USB 44 45 /* I2C */ 46 #define CONFIG_SYS_I2C 47 #define CONFIG_SYS_I2C_MVTWSI 48 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 49 #define CONFIG_SYS_I2C_SLAVE 0x0 50 #define CONFIG_SYS_I2C_SPEED 100000 51 52 /* USB/EHCI configuration */ 53 #define CONFIG_USB_EHCI 54 #define CONFIG_USB_STORAGE 55 #define CONFIG_USB_EHCI_MARVELL 56 #define CONFIG_EHCI_IS_TDI 57 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 58 59 /* SPI NOR flash default params, used by sf commands */ 60 #define CONFIG_SF_DEFAULT_SPEED 1000000 61 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 62 #define CONFIG_SPI_FLASH_STMICRO 63 64 /* Environment in SPI NOR flash */ 65 #define CONFIG_ENV_IS_IN_SPI_FLASH 66 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 67 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 68 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 69 70 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 71 #define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } 72 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII 73 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 74 #define CONFIG_RESET_PHY_R 75 76 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 77 #define CONFIG_SYS_ALT_MEMTEST 78 79 /* SATA support */ 80 #ifdef CONFIG_CMD_IDE 81 #define __io 82 #define CONFIG_IDE_PREINIT 83 #define CONFIG_MVSATA_IDE 84 85 /* Needs byte-swapping for ATA data register */ 86 #define CONFIG_IDE_SWAP_IO 87 88 #define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ 89 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ 90 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 91 92 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 93 #define CONFIG_SYS_ATA_STRIDE 4 94 95 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 96 #define CONFIG_SYS_IDE_MAXBUS 2 97 #define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS 98 99 /* ATA registers base is at SATA controller base */ 100 #define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE 101 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 102 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 103 104 #define CONFIG_DOS_PARTITION 105 #endif /* CONFIG_CMD_IDE */ 106 107 /* PCIe support */ 108 #define CONFIG_PCI 109 #define CONFIG_PCI_MVEBU 110 #define CONFIG_PCI_PNP 111 #define CONFIG_PCI_SCAN_SHOW 112 #define CONFIG_E1000 /* enable Intel E1000 support for testing */ 113 114 /* NAND */ 115 #define CONFIG_SYS_NAND_USE_FLASH_BBT 116 #define CONFIG_SYS_NAND_ONFI_DETECTION 117 118 /* 119 * mv-common.h should be defined after CMD configs since it used them 120 * to enable certain macros 121 */ 122 #include "mv-common.h" 123 124 /* 125 * Memory layout while starting into the bin_hdr via the 126 * BootROM: 127 * 128 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 129 * 0x4000.4030 bin_hdr start address 130 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 131 * 0x4007.fffc BootROM stack top 132 * 133 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 134 * L2 cache thus cannot be used. 135 */ 136 137 /* SPL */ 138 /* Defines for SPL */ 139 #define CONFIG_SPL_FRAMEWORK 140 #define CONFIG_SPL_TEXT_BASE 0x40004030 141 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 142 143 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 144 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 145 146 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 147 CONFIG_SPL_BSS_MAX_SIZE) 148 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 149 150 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 151 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 152 153 #define CONFIG_SPL_LIBCOMMON_SUPPORT 154 #define CONFIG_SPL_LIBGENERIC_SUPPORT 155 #define CONFIG_SPL_SERIAL_SUPPORT 156 #define CONFIG_SPL_I2C_SUPPORT 157 158 /* SPL related SPI defines */ 159 #define CONFIG_SPL_SPI_SUPPORT 160 #define CONFIG_SPL_SPI_FLASH_SUPPORT 161 #define CONFIG_SPL_SPI_LOAD 162 #define CONFIG_SPL_SPI_BUS 0 163 #define CONFIG_SPL_SPI_CS 0 164 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 165 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 166 167 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 168 #define CONFIG_SYS_MVEBU_DDR_AXP 169 #define CONFIG_SPD_EEPROM 0x4e 170 171 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 172