1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 17 /* 18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19 * for DDR ECC byte filling in the SPL before loading the main 20 * U-Boot into it. 21 */ 22 #define CONFIG_SYS_TEXT_BASE 0x00800000 23 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24 25 /* I2C */ 26 #define CONFIG_SYS_I2C 27 #define CONFIG_SYS_I2C_MVTWSI 28 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29 #define CONFIG_SYS_I2C_SLAVE 0x0 30 #define CONFIG_SYS_I2C_SPEED 100000 31 32 /* USB/EHCI configuration */ 33 #define CONFIG_EHCI_IS_TDI 34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 35 36 /* SPI NOR flash default params, used by sf commands */ 37 #define CONFIG_SF_DEFAULT_SPEED 1000000 38 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 39 40 /* Environment in SPI NOR flash */ 41 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 42 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 43 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 44 45 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 46 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 47 48 #define CONFIG_SYS_ALT_MEMTEST 49 50 /* SATA support */ 51 #define CONFIG_SYS_SATA_MAX_DEVICE 2 52 #define CONFIG_LBA48 53 54 /* Additional FS support/configuration */ 55 #define CONFIG_SUPPORT_VFAT 56 57 /* PCIe support */ 58 #ifndef CONFIG_SPL_BUILD 59 #define CONFIG_PCI_MVEBU 60 #define CONFIG_PCI_SCAN_SHOW 61 #endif 62 63 /* NAND */ 64 #define CONFIG_SYS_NAND_USE_FLASH_BBT 65 #define CONFIG_SYS_NAND_ONFI_DETECTION 66 67 /* 68 * mv-common.h should be defined after CMD configs since it used them 69 * to enable certain macros 70 */ 71 #include "mv-common.h" 72 73 /* 74 * Memory layout while starting into the bin_hdr via the 75 * BootROM: 76 * 77 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 78 * 0x4000.4030 bin_hdr start address 79 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 80 * 0x4007.fffc BootROM stack top 81 * 82 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 83 * L2 cache thus cannot be used. 84 */ 85 86 /* SPL */ 87 /* Defines for SPL */ 88 #define CONFIG_SPL_FRAMEWORK 89 #define CONFIG_SPL_TEXT_BASE 0x40004030 90 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 91 92 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 93 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 94 95 #ifdef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MALLOC_SIMPLE 97 #endif 98 99 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 100 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 101 102 /* SPL related SPI defines */ 103 #define CONFIG_SPL_SPI_LOAD 104 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 105 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 106 107 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 108 #define CONFIG_SPD_EEPROM 0x4e 109 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 110 111 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 112