1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef _CONFIG_DB_MV7846MP_GP_H 7 #define _CONFIG_DB_MV7846MP_GP_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 13 14 /* 15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 16 * for DDR ECC byte filling in the SPL before loading the main 17 * U-Boot into it. 18 */ 19 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 20 21 /* I2C */ 22 #define CONFIG_SYS_I2C 23 #define CONFIG_SYS_I2C_MVTWSI 24 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 25 #define CONFIG_SYS_I2C_SLAVE 0x0 26 #define CONFIG_SYS_I2C_SPEED 100000 27 28 /* USB/EHCI configuration */ 29 #define CONFIG_EHCI_IS_TDI 30 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 31 32 /* SPI NOR flash default params, used by sf commands */ 33 #define CONFIG_SF_DEFAULT_SPEED 1000000 34 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 35 36 /* Environment in SPI NOR flash */ 37 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 38 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 39 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 40 41 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 42 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 43 44 /* SATA support */ 45 #define CONFIG_SYS_SATA_MAX_DEVICE 2 46 #define CONFIG_LBA48 47 48 /* PCIe support */ 49 #ifndef CONFIG_SPL_BUILD 50 #define CONFIG_PCI_MVEBU 51 #define CONFIG_PCI_SCAN_SHOW 52 #endif 53 54 /* NAND */ 55 #define CONFIG_SYS_NAND_USE_FLASH_BBT 56 #define CONFIG_SYS_NAND_ONFI_DETECTION 57 58 /* 59 * mv-common.h should be defined after CMD configs since it used them 60 * to enable certain macros 61 */ 62 #include "mv-common.h" 63 64 /* 65 * Memory layout while starting into the bin_hdr via the 66 * BootROM: 67 * 68 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 69 * 0x4000.4030 bin_hdr start address 70 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 71 * 0x4007.fffc BootROM stack top 72 * 73 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 74 * L2 cache thus cannot be used. 75 */ 76 77 /* SPL */ 78 /* Defines for SPL */ 79 #define CONFIG_SPL_TEXT_BASE 0x40004030 80 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 81 82 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 83 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 84 85 #ifdef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MALLOC_SIMPLE 87 #endif 88 89 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 90 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 91 92 /* SPL related SPI defines */ 93 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 94 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 95 96 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 97 #define CONFIG_SPD_EEPROM 0x4e 98 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 99 100 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 101