1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17 #define CONFIG_SYS_GENERIC_BOARD 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 20 #define CONFIG_SYS_TEXT_BASE 0x04000000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 27 #define CONFIG_CMD_DHCP 28 #define CONFIG_CMD_ENV 29 #define CONFIG_CMD_I2C 30 #define CONFIG_CMD_PING 31 #define CONFIG_CMD_SF 32 #define CONFIG_CMD_SPI 33 #define CONFIG_CMD_TFTPPUT 34 #define CONFIG_CMD_TIME 35 36 /* I2C */ 37 #define CONFIG_SYS_I2C 38 #define CONFIG_SYS_I2C_MVTWSI 39 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 40 #define CONFIG_SYS_I2C_SLAVE 0x0 41 #define CONFIG_SYS_I2C_SPEED 100000 42 43 /* SPI NOR flash default params, used by sf commands */ 44 #define CONFIG_SF_DEFAULT_SPEED 1000000 45 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 46 #define CONFIG_SPI_FLASH_STMICRO 47 48 /* Environment in SPI NOR flash */ 49 #define CONFIG_ENV_IS_IN_SPI_FLASH 50 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 51 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 52 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 53 54 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 55 #define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } 56 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII 57 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 58 #define CONFIG_RESET_PHY_R 59 60 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 61 #define CONFIG_SYS_ALT_MEMTEST 62 63 /* 64 * mv-common.h should be defined after CMD configs since it used them 65 * to enable certain macros 66 */ 67 #include "mv-common.h" 68 69 /* 70 * Memory layout while starting into the bin_hdr via the 71 * BootROM: 72 * 73 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 74 * 0x4000.4030 bin_hdr start address 75 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 76 * 0x4007.fffc BootROM stack top 77 * 78 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 79 * L2 cache thus cannot be used. 80 */ 81 82 /* SPL */ 83 /* Defines for SPL */ 84 #define CONFIG_SPL_FRAMEWORK 85 #define CONFIG_SPL_TEXT_BASE 0x40004030 86 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 87 88 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 89 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 90 91 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 92 CONFIG_SPL_BSS_MAX_SIZE) 93 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 94 95 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 96 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 97 98 #define CONFIG_SPL_LIBCOMMON_SUPPORT 99 #define CONFIG_SPL_LIBGENERIC_SUPPORT 100 #define CONFIG_SPL_SERIAL_SUPPORT 101 #define CONFIG_SPL_I2C_SUPPORT 102 103 /* SPL related SPI defines */ 104 #define CONFIG_SPL_SPI_SUPPORT 105 #define CONFIG_SPL_SPI_FLASH_SUPPORT 106 #define CONFIG_SPL_SPI_LOAD 107 #define CONFIG_SPL_SPI_BUS 0 108 #define CONFIG_SPL_SPI_CS 0 109 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 110 111 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 112 #define CONFIG_SYS_MVEBU_DDR 113 #define CONFIG_SPD_EEPROM 0x4e 114 115 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 116