1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6820_GP_H 8 #define _CONFIG_DB_88F6820_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_ARMADA_38X 15 #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ 16 17 #define CONFIG_SYS_L2_PL310 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 20 #define CONFIG_SYS_GENERIC_BOARD 21 #define CONFIG_DISPLAY_BOARDINFO_LATE 22 23 /* 24 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 25 * for DDR ECC byte filling in the SPL before loading the main 26 * U-Boot into it. 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0x00800000 29 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 30 31 /* 32 * Commands configuration 33 */ 34 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 35 #define CONFIG_CMD_CACHE 36 #define CONFIG_CMD_DHCP 37 #define CONFIG_CMD_ENV 38 #define CONFIG_CMD_EXT2 39 #define CONFIG_CMD_EXT4 40 #define CONFIG_CMD_FAT 41 #define CONFIG_CMD_FS_GENERIC 42 #define CONFIG_CMD_I2C 43 #define CONFIG_CMD_MMC 44 #define CONFIG_CMD_PCI 45 #define CONFIG_CMD_PING 46 #define CONFIG_CMD_SCSI 47 #define CONFIG_CMD_SF 48 #define CONFIG_CMD_SPI 49 #define CONFIG_CMD_TFTPPUT 50 #define CONFIG_CMD_TIME 51 #define CONFIG_CMD_USB 52 53 /* I2C */ 54 #define CONFIG_SYS_I2C 55 #define CONFIG_SYS_I2C_MVTWSI 56 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 57 #define CONFIG_SYS_I2C_SLAVE 0x0 58 #define CONFIG_SYS_I2C_SPEED 100000 59 60 /* SPI NOR flash default params, used by sf commands */ 61 #define CONFIG_SF_DEFAULT_SPEED 1000000 62 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 63 #define CONFIG_SPI_FLASH_STMICRO 64 65 /* 66 * SDIO/MMC Card Configuration 67 */ 68 #define CONFIG_MMC 69 #define CONFIG_MMC_SDMA 70 #define CONFIG_GENERIC_MMC 71 #define CONFIG_SDHCI 72 #define CONFIG_MV_SDHCI 73 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 74 75 /* 76 * SATA/SCSI/AHCI configuration 77 */ 78 #define CONFIG_LIBATA 79 #define CONFIG_SCSI_AHCI 80 #define CONFIG_SCSI_AHCI_PLAT 81 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 82 #define CONFIG_SYS_SCSI_MAX_LUN 1 83 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 84 CONFIG_SYS_SCSI_MAX_LUN) 85 86 /* Partition support */ 87 #define CONFIG_DOS_PARTITION 88 #define CONFIG_EFI_PARTITION 89 90 /* Additional FS support/configuration */ 91 #define CONFIG_SUPPORT_VFAT 92 93 /* USB/EHCI configuration */ 94 #define CONFIG_USB_EHCI 95 #define CONFIG_USB_STORAGE 96 #define CONFIG_USB_EHCI_MARVELL 97 #define CONFIG_EHCI_IS_TDI 98 99 /* Environment in SPI NOR flash */ 100 #define CONFIG_ENV_IS_IN_SPI_FLASH 101 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 102 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 103 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 104 105 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 106 #define CONFIG_PHY_ADDR { 1, 0 } 107 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 108 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 109 110 /* PCIe support */ 111 #define CONFIG_PCI 112 #define CONFIG_PCI_MVEBU 113 #define CONFIG_PCI_PNP 114 #define CONFIG_PCI_SCAN_SHOW 115 #define CONFIG_E1000 /* enable Intel E1000 support for testing */ 116 117 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 118 #define CONFIG_SYS_ALT_MEMTEST 119 120 /* Keep device tree and initrd in lower memory so the kernel can access them */ 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "fdt_high=0x10000000\0" \ 123 "initrd_high=0x10000000\0" 124 125 /* SPL */ 126 /* 127 * Select the boot device here 128 * 129 * Currently supported are: 130 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 131 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 132 */ 133 #define SPL_BOOT_SPI_NOR_FLASH 1 134 #define SPL_BOOT_SDIO_MMC_CARD 2 135 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 136 137 /* Defines for SPL */ 138 #define CONFIG_SPL_FRAMEWORK 139 #define CONFIG_SPL_SIZE (140 << 10) 140 #define CONFIG_SPL_TEXT_BASE 0x40000030 141 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 142 143 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 144 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 145 146 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 147 CONFIG_SPL_BSS_MAX_SIZE) 148 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 149 150 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 151 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 152 153 #define CONFIG_SPL_LIBCOMMON_SUPPORT 154 #define CONFIG_SPL_LIBGENERIC_SUPPORT 155 #define CONFIG_SPL_SERIAL_SUPPORT 156 #define CONFIG_SPL_I2C_SUPPORT 157 158 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 159 /* SPL related SPI defines */ 160 #define CONFIG_SPL_SPI_SUPPORT 161 #define CONFIG_SPL_SPI_FLASH_SUPPORT 162 #define CONFIG_SPL_SPI_LOAD 163 #define CONFIG_SPL_SPI_BUS 0 164 #define CONFIG_SPL_SPI_CS 0 165 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 166 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 167 #endif 168 169 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 170 /* SPL related MMC defines */ 171 #define CONFIG_SPL_MMC_SUPPORT 172 #define CONFIG_SPL_LIBDISK_SUPPORT 173 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 174 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) 175 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 176 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 177 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ 178 #ifdef CONFIG_SPL_BUILD 179 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 180 #endif 181 #endif 182 183 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 184 #define CONFIG_SYS_MVEBU_DDR_A38X 185 #define CONFIG_DDR3 186 187 /* 188 * mv-common.h should be defined after CMD configs since it used them 189 * to enable certain macros 190 */ 191 #include "mv-common.h" 192 193 #endif /* _CONFIG_DB_88F6820_GP_H */ 194