1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6820_GP_H 8 #define _CONFIG_DB_88F6820_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_ARMADA_38X 15 #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ 16 17 #define CONFIG_SYS_L2_PL310 18 19 #ifdef CONFIG_SPL_BUILD 20 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 21 #endif 22 #define CONFIG_DISPLAY_BOARDINFO_LATE 23 24 /* 25 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 26 * for DDR ECC byte filling in the SPL before loading the main 27 * U-Boot into it. 28 */ 29 #define CONFIG_SYS_TEXT_BASE 0x00800000 30 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 31 32 /* 33 * Commands configuration 34 */ 35 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 36 #define CONFIG_CMD_CACHE 37 #define CONFIG_CMD_DHCP 38 #define CONFIG_CMD_ENV 39 #define CONFIG_CMD_EXT2 40 #define CONFIG_CMD_EXT4 41 #define CONFIG_CMD_FAT 42 #define CONFIG_CMD_FS_GENERIC 43 #define CONFIG_CMD_I2C 44 #define CONFIG_CMD_MMC 45 #define CONFIG_CMD_PCI 46 #define CONFIG_CMD_PING 47 #define CONFIG_CMD_SCSI 48 #define CONFIG_CMD_SF 49 #define CONFIG_CMD_SPI 50 #define CONFIG_CMD_TFTPPUT 51 #define CONFIG_CMD_TIME 52 53 /* I2C */ 54 #define CONFIG_SYS_I2C 55 #define CONFIG_SYS_I2C_MVTWSI 56 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 57 #define CONFIG_SYS_I2C_SLAVE 0x0 58 #define CONFIG_SYS_I2C_SPEED 100000 59 60 /* SPI NOR flash default params, used by sf commands */ 61 #define CONFIG_SF_DEFAULT_SPEED 1000000 62 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 63 64 /* 65 * SDIO/MMC Card Configuration 66 */ 67 #define CONFIG_MMC 68 #define CONFIG_MMC_SDMA 69 #define CONFIG_GENERIC_MMC 70 #define CONFIG_SDHCI 71 #define CONFIG_MV_SDHCI 72 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 73 74 /* 75 * SATA/SCSI/AHCI configuration 76 */ 77 #define CONFIG_LIBATA 78 #define CONFIG_SCSI_AHCI 79 #define CONFIG_SCSI_AHCI_PLAT 80 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 81 #define CONFIG_SYS_SCSI_MAX_LUN 1 82 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 83 CONFIG_SYS_SCSI_MAX_LUN) 84 85 /* Partition support */ 86 #define CONFIG_DOS_PARTITION 87 #define CONFIG_EFI_PARTITION 88 89 /* Additional FS support/configuration */ 90 #define CONFIG_SUPPORT_VFAT 91 92 /* USB/EHCI configuration */ 93 #define CONFIG_EHCI_IS_TDI 94 95 /* Environment in SPI NOR flash */ 96 #define CONFIG_ENV_IS_IN_SPI_FLASH 97 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 98 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 99 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 100 101 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 102 #define CONFIG_PHY_ADDR { 1, 0 } 103 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 104 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 105 106 /* PCIe support */ 107 #define CONFIG_PCI 108 #define CONFIG_PCI_MVEBU 109 #define CONFIG_PCI_PNP 110 #define CONFIG_PCI_SCAN_SHOW 111 #define CONFIG_E1000 /* enable Intel E1000 support for testing */ 112 113 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 114 #define CONFIG_SYS_ALT_MEMTEST 115 116 /* Keep device tree and initrd in lower memory so the kernel can access them */ 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "fdt_high=0x10000000\0" \ 119 "initrd_high=0x10000000\0" 120 121 /* SPL */ 122 /* 123 * Select the boot device here 124 * 125 * Currently supported are: 126 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 127 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 128 */ 129 #define SPL_BOOT_SPI_NOR_FLASH 1 130 #define SPL_BOOT_SDIO_MMC_CARD 2 131 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 132 133 /* Defines for SPL */ 134 #define CONFIG_SPL_FRAMEWORK 135 #define CONFIG_SPL_SIZE (140 << 10) 136 #define CONFIG_SPL_TEXT_BASE 0x40000030 137 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 138 139 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 140 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 141 142 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 143 CONFIG_SPL_BSS_MAX_SIZE) 144 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 145 146 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 147 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 148 149 #define CONFIG_SPL_LIBCOMMON_SUPPORT 150 #define CONFIG_SPL_LIBGENERIC_SUPPORT 151 #define CONFIG_SPL_SERIAL_SUPPORT 152 #define CONFIG_SPL_I2C_SUPPORT 153 154 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 155 /* SPL related SPI defines */ 156 #define CONFIG_SPL_SPI_SUPPORT 157 #define CONFIG_SPL_SPI_FLASH_SUPPORT 158 #define CONFIG_SPL_SPI_LOAD 159 #define CONFIG_SPL_SPI_BUS 0 160 #define CONFIG_SPL_SPI_CS 0 161 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 162 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 163 #endif 164 165 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 166 /* SPL related MMC defines */ 167 #define CONFIG_SPL_MMC_SUPPORT 168 #define CONFIG_SPL_LIBDISK_SUPPORT 169 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 170 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) 171 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 172 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 173 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ 174 #ifdef CONFIG_SPL_BUILD 175 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 176 #endif 177 #endif 178 179 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 180 #define CONFIG_SYS_MVEBU_DDR_A38X 181 #define CONFIG_DDR3 182 183 /* 184 * mv-common.h should be defined after CMD configs since it used them 185 * to enable certain macros 186 */ 187 #include "mv-common.h" 188 189 #endif /* _CONFIG_DB_88F6820_GP_H */ 190