1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6820_GP_H 8 #define _CONFIG_DB_88F6820_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_ARMADA_38X 15 #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ 16 17 #define CONFIG_DISPLAY_BOARDINFO_LATE 18 19 /* 20 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 21 * for DDR ECC byte filling in the SPL before loading the main 22 * U-Boot into it. 23 */ 24 #define CONFIG_SYS_TEXT_BASE 0x00800000 25 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 26 27 /* 28 * Commands configuration 29 */ 30 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 31 #define CONFIG_CMD_CACHE 32 #define CONFIG_CMD_DHCP 33 #define CONFIG_CMD_ENV 34 #define CONFIG_CMD_EXT2 35 #define CONFIG_CMD_EXT4 36 #define CONFIG_CMD_FAT 37 #define CONFIG_CMD_FS_GENERIC 38 #define CONFIG_CMD_I2C 39 #define CONFIG_CMD_MMC 40 #define CONFIG_CMD_PCI 41 #define CONFIG_CMD_PING 42 #define CONFIG_CMD_SCSI 43 #define CONFIG_CMD_SF 44 #define CONFIG_CMD_SPI 45 #define CONFIG_CMD_TFTPPUT 46 #define CONFIG_CMD_TIME 47 48 /* I2C */ 49 #define CONFIG_SYS_I2C 50 #define CONFIG_SYS_I2C_MVTWSI 51 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 52 #define CONFIG_SYS_I2C_SLAVE 0x0 53 #define CONFIG_SYS_I2C_SPEED 100000 54 55 /* SPI NOR flash default params, used by sf commands */ 56 #define CONFIG_SF_DEFAULT_SPEED 1000000 57 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 58 59 /* 60 * SDIO/MMC Card Configuration 61 */ 62 #define CONFIG_MMC 63 #define CONFIG_MMC_SDMA 64 #define CONFIG_GENERIC_MMC 65 #define CONFIG_SDHCI 66 #define CONFIG_MV_SDHCI 67 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 68 69 /* 70 * SATA/SCSI/AHCI configuration 71 */ 72 #define CONFIG_LIBATA 73 #define CONFIG_SCSI_AHCI 74 #define CONFIG_SCSI_AHCI_PLAT 75 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 76 #define CONFIG_SYS_SCSI_MAX_LUN 1 77 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 78 CONFIG_SYS_SCSI_MAX_LUN) 79 80 /* Partition support */ 81 #define CONFIG_DOS_PARTITION 82 #define CONFIG_EFI_PARTITION 83 84 /* Additional FS support/configuration */ 85 #define CONFIG_SUPPORT_VFAT 86 87 /* USB/EHCI configuration */ 88 #define CONFIG_EHCI_IS_TDI 89 90 /* Environment in SPI NOR flash */ 91 #define CONFIG_ENV_IS_IN_SPI_FLASH 92 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 93 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 94 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 95 96 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 97 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 98 99 /* PCIe support */ 100 #ifndef CONFIG_SPL_BUILD 101 #define CONFIG_PCI 102 #define CONFIG_PCI_MVEBU 103 #define CONFIG_PCI_PNP 104 #define CONFIG_PCI_SCAN_SHOW 105 #endif 106 107 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 108 #define CONFIG_SYS_ALT_MEMTEST 109 110 /* Keep device tree and initrd in lower memory so the kernel can access them */ 111 #define CONFIG_EXTRA_ENV_SETTINGS \ 112 "fdt_high=0x10000000\0" \ 113 "initrd_high=0x10000000\0" 114 115 /* SPL */ 116 /* 117 * Select the boot device here 118 * 119 * Currently supported are: 120 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 121 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 122 */ 123 #define SPL_BOOT_SPI_NOR_FLASH 1 124 #define SPL_BOOT_SDIO_MMC_CARD 2 125 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 126 127 /* Defines for SPL */ 128 #define CONFIG_SPL_FRAMEWORK 129 #define CONFIG_SPL_SIZE (140 << 10) 130 #define CONFIG_SPL_TEXT_BASE 0x40000030 131 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 132 133 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 134 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 135 136 #ifdef CONFIG_SPL_BUILD 137 #define CONFIG_SYS_MALLOC_SIMPLE 138 #endif 139 140 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 141 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 142 143 #define CONFIG_SPL_LIBCOMMON_SUPPORT 144 #define CONFIG_SPL_LIBGENERIC_SUPPORT 145 #define CONFIG_SPL_SERIAL_SUPPORT 146 #define CONFIG_SPL_I2C_SUPPORT 147 148 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 149 /* SPL related SPI defines */ 150 #define CONFIG_SPL_SPI_SUPPORT 151 #define CONFIG_SPL_SPI_FLASH_SUPPORT 152 #define CONFIG_SPL_SPI_LOAD 153 #define CONFIG_SPL_SPI_BUS 0 154 #define CONFIG_SPL_SPI_CS 0 155 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 156 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 157 #endif 158 159 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 160 /* SPL related MMC defines */ 161 #define CONFIG_SPL_MMC_SUPPORT 162 #define CONFIG_SPL_LIBDISK_SUPPORT 163 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 164 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) 165 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 166 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 167 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ 168 #ifdef CONFIG_SPL_BUILD 169 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 170 #endif 171 #endif 172 173 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 174 #define CONFIG_SYS_MVEBU_DDR_A38X 175 #define CONFIG_DDR3 176 177 /* 178 * mv-common.h should be defined after CMD configs since it used them 179 * to enable certain macros 180 */ 181 #include "mv-common.h" 182 183 #endif /* _CONFIG_DB_88F6820_GP_H */ 184