1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6720_H 8 #define _CONFIG_DB_88F6720_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 27 #define CONFIG_CMD_ENV 28 29 /* I2C */ 30 #define CONFIG_SYS_I2C 31 #define CONFIG_SYS_I2C_MVTWSI 32 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 33 #define CONFIG_SYS_I2C_SLAVE 0x0 34 #define CONFIG_SYS_I2C_SPEED 100000 35 36 /* USB/EHCI configuration */ 37 #define CONFIG_EHCI_IS_TDI 38 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 39 40 /* SPI NOR flash default params, used by sf commands */ 41 #define CONFIG_SF_DEFAULT_SPEED 1000000 42 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 43 44 /* Environment in SPI NOR flash */ 45 #define CONFIG_ENV_IS_IN_SPI_FLASH 46 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 47 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 48 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 49 50 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 51 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 52 53 #define CONFIG_SYS_ALT_MEMTEST 54 55 /* Additional FS support/configuration */ 56 #define CONFIG_SUPPORT_VFAT 57 58 /* 59 * mv-common.h should be defined after CMD configs since it used them 60 * to enable certain macros 61 */ 62 #include "mv-common.h" 63 64 /* 65 * Memory layout while starting into the bin_hdr via the 66 * BootROM: 67 * 68 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 69 * 0x4000.4030 bin_hdr start address 70 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 71 * 0x4007.fffc BootROM stack top 72 * 73 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 74 * L2 cache thus cannot be used. 75 */ 76 77 /* SPL */ 78 /* Defines for SPL */ 79 #define CONFIG_SPL_FRAMEWORK 80 #define CONFIG_SPL_TEXT_BASE 0x40004030 81 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 82 83 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 84 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 85 86 #ifdef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MALLOC_SIMPLE 88 #endif 89 90 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 91 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 92 93 /* SPL related SPI defines */ 94 #define CONFIG_SPL_SPI_LOAD 95 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 96 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 97 98 #endif /* _CONFIG_DB_88F6720_H */ 99