1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6720_H 8 #define _CONFIG_DB_88F6720_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 14 /* 15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 16 * for DDR ECC byte filling in the SPL before loading the main 17 * U-Boot into it. 18 */ 19 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 20 21 /* 22 * Commands configuration 23 */ 24 25 /* I2C */ 26 #define CONFIG_SYS_I2C 27 #define CONFIG_SYS_I2C_MVTWSI 28 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29 #define CONFIG_SYS_I2C_SLAVE 0x0 30 #define CONFIG_SYS_I2C_SPEED 100000 31 32 /* USB/EHCI configuration */ 33 #define CONFIG_EHCI_IS_TDI 34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 35 36 /* SPI NOR flash default params, used by sf commands */ 37 #define CONFIG_SF_DEFAULT_SPEED 1000000 38 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 39 40 /* Environment in SPI NOR flash */ 41 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 42 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 43 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 44 45 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 46 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 47 48 /* 49 * mv-common.h should be defined after CMD configs since it used them 50 * to enable certain macros 51 */ 52 #include "mv-common.h" 53 54 /* 55 * Memory layout while starting into the bin_hdr via the 56 * BootROM: 57 * 58 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 59 * 0x4000.4030 bin_hdr start address 60 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 61 * 0x4007.fffc BootROM stack top 62 * 63 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 64 * L2 cache thus cannot be used. 65 */ 66 67 /* SPL */ 68 /* Defines for SPL */ 69 #define CONFIG_SPL_TEXT_BASE 0x40004030 70 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 71 72 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 73 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 74 75 #ifdef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MALLOC_SIMPLE 77 #endif 78 79 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 80 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 81 82 /* SPL related SPI defines */ 83 #define CONFIG_SPL_SPI_LOAD 84 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 85 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 86 87 #endif /* _CONFIG_DB_88F6720_H */ 88