1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef _CONFIG_DB_88F6720_H 7 #define _CONFIG_DB_88F6720_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 13 /* 14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 15 * for DDR ECC byte filling in the SPL before loading the main 16 * U-Boot into it. 17 */ 18 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 19 20 /* 21 * Commands configuration 22 */ 23 24 /* I2C */ 25 #define CONFIG_SYS_I2C 26 #define CONFIG_SYS_I2C_MVTWSI 27 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 28 #define CONFIG_SYS_I2C_SLAVE 0x0 29 #define CONFIG_SYS_I2C_SPEED 100000 30 31 /* USB/EHCI configuration */ 32 #define CONFIG_EHCI_IS_TDI 33 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 34 35 /* SPI NOR flash default params, used by sf commands */ 36 #define CONFIG_SF_DEFAULT_SPEED 1000000 37 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 38 39 /* Environment in SPI NOR flash */ 40 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 41 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 42 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 43 44 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 45 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 46 47 /* 48 * mv-common.h should be defined after CMD configs since it used them 49 * to enable certain macros 50 */ 51 #include "mv-common.h" 52 53 /* 54 * Memory layout while starting into the bin_hdr via the 55 * BootROM: 56 * 57 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 58 * 0x4000.4030 bin_hdr start address 59 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 60 * 0x4007.fffc BootROM stack top 61 * 62 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 63 * L2 cache thus cannot be used. 64 */ 65 66 /* SPL */ 67 /* Defines for SPL */ 68 #define CONFIG_SPL_TEXT_BASE 0x40004030 69 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 70 71 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 72 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 73 74 #ifdef CONFIG_SPL_BUILD 75 #define CONFIG_SYS_MALLOC_SIMPLE 76 #endif 77 78 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 79 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 80 81 /* SPL related SPI defines */ 82 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 83 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 84 85 #endif /* _CONFIG_DB_88F6720_H */ 86