1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6720_H 8 #define _CONFIG_DB_88F6720_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 21 22 /* 23 * Commands configuration 24 */ 25 26 /* I2C */ 27 #define CONFIG_SYS_I2C 28 #define CONFIG_SYS_I2C_MVTWSI 29 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 30 #define CONFIG_SYS_I2C_SLAVE 0x0 31 #define CONFIG_SYS_I2C_SPEED 100000 32 33 /* USB/EHCI configuration */ 34 #define CONFIG_EHCI_IS_TDI 35 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 36 37 /* SPI NOR flash default params, used by sf commands */ 38 #define CONFIG_SF_DEFAULT_SPEED 1000000 39 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 40 41 /* Environment in SPI NOR flash */ 42 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 43 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 44 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 45 46 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 47 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 48 49 #define CONFIG_SYS_ALT_MEMTEST 50 51 /* 52 * mv-common.h should be defined after CMD configs since it used them 53 * to enable certain macros 54 */ 55 #include "mv-common.h" 56 57 /* 58 * Memory layout while starting into the bin_hdr via the 59 * BootROM: 60 * 61 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 62 * 0x4000.4030 bin_hdr start address 63 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 64 * 0x4007.fffc BootROM stack top 65 * 66 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 67 * L2 cache thus cannot be used. 68 */ 69 70 /* SPL */ 71 /* Defines for SPL */ 72 #define CONFIG_SPL_TEXT_BASE 0x40004030 73 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 74 75 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 76 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 77 78 #ifdef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MALLOC_SIMPLE 80 #endif 81 82 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 83 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 84 85 /* SPL related SPI defines */ 86 #define CONFIG_SPL_SPI_LOAD 87 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 88 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 89 90 #endif /* _CONFIG_DB_88F6720_H */ 91