1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2606576d5SStefan Roese /* 3606576d5SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4606576d5SStefan Roese */ 5606576d5SStefan Roese 6606576d5SStefan Roese #ifndef _CONFIG_DB_88F6720_H 7606576d5SStefan Roese #define _CONFIG_DB_88F6720_H 8606576d5SStefan Roese 9606576d5SStefan Roese /* 10606576d5SStefan Roese * High Level Configuration Options (easy to change) 11606576d5SStefan Roese */ 12606576d5SStefan Roese 13606576d5SStefan Roese /* 14606576d5SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 15606576d5SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 16606576d5SStefan Roese * U-Boot into it. 17606576d5SStefan Roese */ 18606576d5SStefan Roese #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 19606576d5SStefan Roese 20606576d5SStefan Roese /* 21606576d5SStefan Roese * Commands configuration 22606576d5SStefan Roese */ 23606576d5SStefan Roese 24606576d5SStefan Roese /* I2C */ 25606576d5SStefan Roese #define CONFIG_SYS_I2C 26606576d5SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 27606576d5SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 28606576d5SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 29606576d5SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 30606576d5SStefan Roese 31606576d5SStefan Roese /* USB/EHCI configuration */ 32606576d5SStefan Roese #define CONFIG_EHCI_IS_TDI 33606576d5SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 34606576d5SStefan Roese 35606576d5SStefan Roese /* SPI NOR flash default params, used by sf commands */ 36606576d5SStefan Roese 37606576d5SStefan Roese /* Environment in SPI NOR flash */ 38606576d5SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 39606576d5SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 40606576d5SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 41606576d5SStefan Roese 42606576d5SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 43606576d5SStefan Roese 44606576d5SStefan Roese /* 45606576d5SStefan Roese * mv-common.h should be defined after CMD configs since it used them 46606576d5SStefan Roese * to enable certain macros 47606576d5SStefan Roese */ 48606576d5SStefan Roese #include "mv-common.h" 49606576d5SStefan Roese 50606576d5SStefan Roese /* 51606576d5SStefan Roese * Memory layout while starting into the bin_hdr via the 52606576d5SStefan Roese * BootROM: 53606576d5SStefan Roese * 54606576d5SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 55606576d5SStefan Roese * 0x4000.4030 bin_hdr start address 56606576d5SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 57606576d5SStefan Roese * 0x4007.fffc BootROM stack top 58606576d5SStefan Roese * 59606576d5SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 60606576d5SStefan Roese * L2 cache thus cannot be used. 61606576d5SStefan Roese */ 62606576d5SStefan Roese 63606576d5SStefan Roese /* SPL */ 64606576d5SStefan Roese /* Defines for SPL */ 65606576d5SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 66606576d5SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 67606576d5SStefan Roese 68606576d5SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 69606576d5SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 70606576d5SStefan Roese 71606576d5SStefan Roese #ifdef CONFIG_SPL_BUILD 72606576d5SStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 73606576d5SStefan Roese #endif 74606576d5SStefan Roese 75606576d5SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 76606576d5SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 77606576d5SStefan Roese 78606576d5SStefan Roese /* SPL related SPI defines */ 79606576d5SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 80606576d5SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 81606576d5SStefan Roese 82606576d5SStefan Roese #endif /* _CONFIG_DB_88F6720_H */ 83