1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 24 /* 25 * SoC Configuration 26 */ 27 #define CONFIG_MACH_DAVINCI_DA850_EVM 28 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 29 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 31 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 32 #define CONFIG_SYS_OSCIN_FREQ 24000000 33 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 34 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 35 #define CONFIG_SYS_DA850_PLL_INIT 36 #define CONFIG_SYS_DA850_DDR_INIT 37 38 #ifdef CONFIG_DIRECT_NOR_BOOT 39 #define CONFIG_ARCH_CPU_INIT 40 #define CONFIG_DA8XX_GPIO 41 #define CONFIG_SYS_TEXT_BASE 0x60000000 42 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 43 #define CONFIG_DA850_LOWLEVEL 44 #else 45 #define CONFIG_SYS_TEXT_BASE 0xc1080000 46 #endif 47 48 /* 49 * Memory Info 50 */ 51 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 52 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 53 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 54 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 55 56 /* memtest start addr */ 57 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 58 59 /* memtest will be run on 16MB */ 60 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 61 62 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 63 64 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 65 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 66 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 67 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 68 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 69 DAVINCI_SYSCFG_SUSPSRC_I2C) 70 71 /* 72 * PLL configuration 73 */ 74 #define CONFIG_SYS_DV_CLKMODE 0 75 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 76 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 77 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 78 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 79 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 80 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 81 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 82 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 83 84 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 85 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 86 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 87 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 88 89 #define CONFIG_SYS_DA850_PLL0_PLLM 24 90 #define CONFIG_SYS_DA850_PLL1_PLLM 21 91 92 /* 93 * DDR2 memory configuration 94 */ 95 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 96 DV_DDR_PHY_EXT_STRBEN | \ 97 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 98 99 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 100 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 101 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 102 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 103 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 104 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 105 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 106 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 107 108 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 109 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 110 111 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 112 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 113 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 114 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 115 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 116 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 117 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 118 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 119 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 120 121 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 122 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 123 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 124 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 125 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 126 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 127 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 128 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 129 130 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 131 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 132 133 /* 134 * Serial Driver info 135 */ 136 #define CONFIG_SYS_NS16550 137 #define CONFIG_SYS_NS16550_SERIAL 138 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 139 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 140 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 141 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 142 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 143 144 #define CONFIG_SPI 145 #define CONFIG_SPI_FLASH 146 #define CONFIG_SPI_FLASH_STMICRO 147 #define CONFIG_SPI_FLASH_WINBOND 148 #define CONFIG_CMD_SF 149 #define CONFIG_DAVINCI_SPI 150 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 151 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 152 #define CONFIG_SF_DEFAULT_SPEED 30000000 153 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 154 155 #ifdef CONFIG_USE_SPIFLASH 156 #define CONFIG_SPL_SPI_SUPPORT 157 #define CONFIG_SPL_SPI_FLASH_SUPPORT 158 #define CONFIG_SPL_SPI_LOAD 159 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 160 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 161 #endif 162 163 /* 164 * I2C Configuration 165 */ 166 #define CONFIG_SYS_I2C 167 #define CONFIG_SYS_I2C_DAVINCI 168 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 169 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 170 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 171 172 /* 173 * Flash & Environment 174 */ 175 #ifdef CONFIG_USE_NAND 176 #undef CONFIG_ENV_IS_IN_FLASH 177 #define CONFIG_NAND_DAVINCI 178 #define CONFIG_SYS_NO_FLASH 179 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 180 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 181 #define CONFIG_ENV_SIZE (128 << 10) 182 #define CONFIG_SYS_NAND_USE_FLASH_BBT 183 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 184 #define CONFIG_SYS_NAND_PAGE_2K 185 #define CONFIG_SYS_NAND_CS 3 186 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 187 #define CONFIG_SYS_NAND_MASK_CLE 0x10 188 #define CONFIG_SYS_NAND_MASK_ALE 0x8 189 #undef CONFIG_SYS_NAND_HW_ECC 190 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 191 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 192 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 193 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 194 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 195 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 196 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 197 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 198 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 199 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 200 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 201 CONFIG_SYS_MALLOC_LEN - \ 202 GENERATED_GBL_DATA_SIZE) 203 #define CONFIG_SYS_NAND_ECCPOS { \ 204 24, 25, 26, 27, 28, \ 205 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 206 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 207 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 208 59, 60, 61, 62, 63 } 209 #define CONFIG_SYS_NAND_PAGE_COUNT 64 210 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 211 #define CONFIG_SYS_NAND_ECCSIZE 512 212 #define CONFIG_SYS_NAND_ECCBYTES 10 213 #define CONFIG_SYS_NAND_OOBSIZE 64 214 #define CONFIG_SPL_NAND_SUPPORT 215 #define CONFIG_SPL_NAND_BASE 216 #define CONFIG_SPL_NAND_DRIVERS 217 #define CONFIG_SPL_NAND_ECC 218 #define CONFIG_SPL_NAND_SIMPLE 219 #define CONFIG_SPL_NAND_LOAD 220 #endif 221 222 /* 223 * Network & Ethernet Configuration 224 */ 225 #ifdef CONFIG_DRIVER_TI_EMAC 226 #define CONFIG_MII 227 #define CONFIG_BOOTP_DNS 228 #define CONFIG_BOOTP_DNS2 229 #define CONFIG_BOOTP_SEND_HOSTNAME 230 #define CONFIG_NET_RETRY_COUNT 10 231 #endif 232 233 #ifdef CONFIG_USE_NOR 234 #define CONFIG_ENV_IS_IN_FLASH 235 #define CONFIG_FLASH_CFI_DRIVER 236 #define CONFIG_SYS_FLASH_CFI 237 #define CONFIG_SYS_FLASH_PROTECTION 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 239 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 240 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 241 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 242 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 243 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 244 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 245 + 3) 246 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 247 #endif 248 249 #ifdef CONFIG_USE_SPIFLASH 250 #undef CONFIG_ENV_IS_IN_FLASH 251 #undef CONFIG_ENV_IS_IN_NAND 252 #define CONFIG_ENV_IS_IN_SPI_FLASH 253 #define CONFIG_ENV_SIZE (64 << 10) 254 #define CONFIG_ENV_OFFSET (512 << 10) 255 #define CONFIG_ENV_SECT_SIZE (64 << 10) 256 #define CONFIG_SYS_NO_FLASH 257 #endif 258 259 /* 260 * U-Boot general configuration 261 */ 262 #define CONFIG_SYS_GENERIC_BOARD 263 #define CONFIG_MISC_INIT_R 264 #define CONFIG_BOARD_EARLY_INIT_F 265 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 266 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ 267 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 268 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 269 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 271 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 272 #define CONFIG_VERSION_VARIABLE 273 #define CONFIG_AUTO_COMPLETE 274 #define CONFIG_SYS_HUSH_PARSER 275 #define CONFIG_CMDLINE_EDITING 276 #define CONFIG_SYS_LONGHELP 277 #define CONFIG_CRC32_VERIFY 278 #define CONFIG_MX_CYCLIC 279 #define CONFIG_OF_LIBFDT 280 281 /* 282 * Linux Information 283 */ 284 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 285 #define CONFIG_HWCONFIG /* enable hwconfig */ 286 #define CONFIG_CMDLINE_TAG 287 #define CONFIG_REVISION_TAG 288 #define CONFIG_SETUP_MEMORY_TAGS 289 #define CONFIG_BOOTARGS \ 290 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" 291 #define CONFIG_BOOTDELAY 3 292 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" 293 294 /* 295 * U-Boot commands 296 */ 297 #include <config_cmd_default.h> 298 #define CONFIG_CMD_ENV 299 #define CONFIG_CMD_ASKENV 300 #define CONFIG_CMD_DHCP 301 #define CONFIG_CMD_DIAG 302 #define CONFIG_CMD_MII 303 #define CONFIG_CMD_PING 304 #define CONFIG_CMD_SAVES 305 #define CONFIG_CMD_MEMORY 306 307 #ifdef CONFIG_CMD_BDI 308 #define CONFIG_CLOCKS 309 #endif 310 311 #ifndef CONFIG_DRIVER_TI_EMAC 312 #undef CONFIG_CMD_NET 313 #undef CONFIG_CMD_DHCP 314 #undef CONFIG_CMD_MII 315 #undef CONFIG_CMD_PING 316 #endif 317 318 #ifdef CONFIG_USE_NAND 319 #undef CONFIG_CMD_FLASH 320 #undef CONFIG_CMD_IMLS 321 #define CONFIG_CMD_NAND 322 323 #define CONFIG_CMD_MTDPARTS 324 #define CONFIG_MTD_DEVICE 325 #define CONFIG_MTD_PARTITIONS 326 #define CONFIG_LZO 327 #define CONFIG_RBTREE 328 #define CONFIG_CMD_UBI 329 #define CONFIG_CMD_UBIFS 330 #endif 331 332 #ifdef CONFIG_USE_SPIFLASH 333 #undef CONFIG_CMD_IMLS 334 #undef CONFIG_CMD_FLASH 335 #define CONFIG_CMD_SPI 336 #define CONFIG_CMD_SAVEENV 337 #endif 338 339 #if !defined(CONFIG_USE_NAND) && \ 340 !defined(CONFIG_USE_NOR) && \ 341 !defined(CONFIG_USE_SPIFLASH) 342 #define CONFIG_ENV_IS_NOWHERE 343 #define CONFIG_SYS_NO_FLASH 344 #define CONFIG_ENV_SIZE (16 << 10) 345 #undef CONFIG_CMD_IMLS 346 #undef CONFIG_CMD_ENV 347 #endif 348 349 /* SD/MMC configuration */ 350 #ifndef CONFIG_USE_NOR 351 #define CONFIG_MMC 352 #define CONFIG_DAVINCI_MMC_SD1 353 #define CONFIG_GENERIC_MMC 354 #define CONFIG_DAVINCI_MMC 355 #endif 356 357 /* 358 * Enable MMC commands only when 359 * MMC support is present 360 */ 361 #ifdef CONFIG_MMC 362 #define CONFIG_DOS_PARTITION 363 #define CONFIG_CMD_EXT2 364 #define CONFIG_CMD_FAT 365 #define CONFIG_CMD_MMC 366 #endif 367 368 #ifndef CONFIG_DIRECT_NOR_BOOT 369 /* defines for SPL */ 370 #define CONFIG_SPL_FRAMEWORK 371 #define CONFIG_SPL_BOARD_INIT 372 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 373 CONFIG_SYS_MALLOC_LEN) 374 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 375 #define CONFIG_SPL_SPI_SUPPORT 376 #define CONFIG_SPL_SPI_FLASH_SUPPORT 377 #define CONFIG_SPL_SPI_LOAD 378 #define CONFIG_SPL_SERIAL_SUPPORT 379 #define CONFIG_SPL_LIBCOMMON_SUPPORT 380 #define CONFIG_SPL_LIBGENERIC_SUPPORT 381 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" 382 #define CONFIG_SPL_STACK 0x8001ff00 383 #define CONFIG_SPL_TEXT_BASE 0x80000000 384 #define CONFIG_SPL_MAX_FOOTPRINT 32768 385 #define CONFIG_SPL_PAD_TO 32768 386 #endif 387 388 /* Load U-Boot Image From MMC */ 389 #ifdef CONFIG_SPL_MMC_LOAD 390 #define CONFIG_SPL_MMC_SUPPORT 391 #define CONFIG_SPL_LIBDISK_SUPPORT 392 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 393 #undef CONFIG_SPL_SPI_SUPPORT 394 #undef CONFIG_SPL_SPI_LOAD 395 #endif 396 397 /* additions for new relocation code, must added to all boards */ 398 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 399 400 #ifdef CONFIG_DIRECT_NOR_BOOT 401 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 402 #else 403 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 404 GENERATED_GBL_DATA_SIZE) 405 #endif /* CONFIG_DIRECT_NOR_BOOT */ 406 #endif /* __CONFIG_H */ 407