1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 /* 24 * SoC Configuration 25 */ 26 #define CONFIG_MACH_DAVINCI_DA850_EVM 27 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 28 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 29 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 30 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 31 #define CONFIG_SYS_OSCIN_FREQ 24000000 32 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 33 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 34 35 #ifdef CONFIG_DIRECT_NOR_BOOT 36 #define CONFIG_ARCH_CPU_INIT 37 #define CONFIG_DA8XX_GPIO 38 #define CONFIG_SYS_TEXT_BASE 0x60000000 39 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 40 #define CONFIG_DA850_LOWLEVEL 41 #else 42 #define CONFIG_SYS_TEXT_BASE 0xc1080000 43 #endif 44 45 /* 46 * Memory Info 47 */ 48 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 49 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 50 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 51 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 52 53 /* memtest start addr */ 54 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 55 56 /* memtest will be run on 16MB */ 57 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 58 59 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 60 61 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 62 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 63 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 64 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 65 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 66 DAVINCI_SYSCFG_SUSPSRC_I2C) 67 68 /* 69 * PLL configuration 70 */ 71 #define CONFIG_SYS_DV_CLKMODE 0 72 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 73 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 74 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 75 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 76 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 77 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 78 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 79 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 80 81 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 82 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 83 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 84 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 85 86 #define CONFIG_SYS_DA850_PLL0_PLLM 24 87 #define CONFIG_SYS_DA850_PLL1_PLLM 21 88 89 /* 90 * DDR2 memory configuration 91 */ 92 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 93 DV_DDR_PHY_EXT_STRBEN | \ 94 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 95 96 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 97 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 98 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 99 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 100 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 101 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 102 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 103 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 104 105 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 106 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 107 108 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 109 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 110 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 111 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 112 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 113 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 114 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 115 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 116 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 117 118 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 119 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 120 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 121 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 122 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 123 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 124 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 125 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 126 127 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 128 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 129 130 /* 131 * Serial Driver info 132 */ 133 #define CONFIG_SYS_NS16550_SERIAL 134 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 135 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 136 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 137 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 138 139 #define CONFIG_SPI 140 #define CONFIG_DAVINCI_SPI 141 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 142 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 143 #define CONFIG_SF_DEFAULT_SPEED 30000000 144 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 145 146 #ifdef CONFIG_USE_SPIFLASH 147 #define CONFIG_SPL_SPI_LOAD 148 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 149 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 150 #endif 151 152 /* 153 * I2C Configuration 154 */ 155 #define CONFIG_SYS_I2C 156 #define CONFIG_SYS_I2C_DAVINCI 157 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 158 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 159 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 160 161 /* 162 * Flash & Environment 163 */ 164 #ifdef CONFIG_USE_NAND 165 #define CONFIG_NAND_DAVINCI 166 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 167 #define CONFIG_ENV_SIZE (128 << 10) 168 #define CONFIG_SYS_NAND_USE_FLASH_BBT 169 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 170 #define CONFIG_SYS_NAND_PAGE_2K 171 #define CONFIG_SYS_NAND_CS 3 172 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 173 #define CONFIG_SYS_NAND_MASK_CLE 0x10 174 #define CONFIG_SYS_NAND_MASK_ALE 0x8 175 #undef CONFIG_SYS_NAND_HW_ECC 176 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 177 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 178 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 179 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 180 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 181 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 182 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 183 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 184 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 185 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 186 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 187 CONFIG_SYS_MALLOC_LEN - \ 188 GENERATED_GBL_DATA_SIZE) 189 #define CONFIG_SYS_NAND_ECCPOS { \ 190 24, 25, 26, 27, 28, \ 191 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 192 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 193 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 194 59, 60, 61, 62, 63 } 195 #define CONFIG_SYS_NAND_PAGE_COUNT 64 196 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 197 #define CONFIG_SYS_NAND_ECCSIZE 512 198 #define CONFIG_SYS_NAND_ECCBYTES 10 199 #define CONFIG_SYS_NAND_OOBSIZE 64 200 #define CONFIG_SPL_NAND_BASE 201 #define CONFIG_SPL_NAND_DRIVERS 202 #define CONFIG_SPL_NAND_ECC 203 #define CONFIG_SPL_NAND_SIMPLE 204 #define CONFIG_SPL_NAND_LOAD 205 #endif 206 207 /* 208 * Network & Ethernet Configuration 209 */ 210 #ifdef CONFIG_DRIVER_TI_EMAC 211 #define CONFIG_MII 212 #define CONFIG_BOOTP_DNS 213 #define CONFIG_BOOTP_DNS2 214 #define CONFIG_BOOTP_SEND_HOSTNAME 215 #define CONFIG_NET_RETRY_COUNT 10 216 #endif 217 218 #ifdef CONFIG_USE_NOR 219 #define CONFIG_FLASH_CFI_DRIVER 220 #define CONFIG_SYS_FLASH_CFI 221 #define CONFIG_SYS_FLASH_PROTECTION 222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 223 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 224 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 225 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 226 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 227 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 228 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 229 + 3) 230 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 231 #endif 232 233 #ifdef CONFIG_USE_SPIFLASH 234 #define CONFIG_ENV_SIZE (64 << 10) 235 #define CONFIG_ENV_OFFSET (512 << 10) 236 #define CONFIG_ENV_SECT_SIZE (64 << 10) 237 #endif 238 239 /* 240 * U-Boot general configuration 241 */ 242 #define CONFIG_MISC_INIT_R 243 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 244 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 245 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 246 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 247 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 248 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 249 #define CONFIG_AUTO_COMPLETE 250 #define CONFIG_CMDLINE_EDITING 251 #define CONFIG_SYS_LONGHELP 252 #define CONFIG_MX_CYCLIC 253 254 /* 255 * Linux Information 256 */ 257 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 258 #define CONFIG_HWCONFIG /* enable hwconfig */ 259 #define CONFIG_CMDLINE_TAG 260 #define CONFIG_REVISION_TAG 261 #define CONFIG_SETUP_MEMORY_TAGS 262 #define CONFIG_BOOTARGS \ 263 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" 264 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" 265 266 /* 267 * U-Boot commands 268 */ 269 #define CONFIG_CMD_SAVES 270 271 #ifdef CONFIG_CMD_BDI 272 #define CONFIG_CLOCKS 273 #endif 274 275 #ifndef CONFIG_DRIVER_TI_EMAC 276 #endif 277 278 #ifdef CONFIG_USE_NAND 279 #define CONFIG_MTD_DEVICE 280 #define CONFIG_MTD_PARTITIONS 281 #endif 282 283 #ifdef CONFIG_USE_SPIFLASH 284 #endif 285 286 #if !defined(CONFIG_USE_NAND) && \ 287 !defined(CONFIG_USE_NOR) && \ 288 !defined(CONFIG_USE_SPIFLASH) 289 #define CONFIG_ENV_SIZE (16 << 10) 290 #endif 291 292 #ifndef CONFIG_DIRECT_NOR_BOOT 293 /* defines for SPL */ 294 #define CONFIG_SPL_FRAMEWORK 295 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 296 CONFIG_SYS_MALLOC_LEN) 297 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 298 #define CONFIG_SPL_SPI_LOAD 299 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" 300 #define CONFIG_SPL_STACK 0x8001ff00 301 #define CONFIG_SPL_TEXT_BASE 0x80000000 302 #define CONFIG_SPL_MAX_FOOTPRINT 32768 303 #define CONFIG_SPL_PAD_TO 32768 304 #endif 305 306 /* Load U-Boot Image From MMC */ 307 #ifdef CONFIG_SPL_MMC_LOAD 308 #undef CONFIG_SPL_SPI_LOAD 309 #endif 310 311 /* additions for new relocation code, must added to all boards */ 312 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 313 314 #ifdef CONFIG_DIRECT_NOR_BOOT 315 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 316 #else 317 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 318 GENERATED_GBL_DATA_SIZE) 319 #endif /* CONFIG_DIRECT_NOR_BOOT */ 320 321 #include <asm/arch/hardware.h> 322 323 #endif /* __CONFIG_H */ 324