1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on davinci_dvevm.h. Original Copyrights follow: 6 * 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * Board 15 */ 16 /* check if direct NOR boot config is used */ 17 #ifndef CONFIG_DIRECT_NOR_BOOT 18 #define CONFIG_USE_SPIFLASH 19 #endif 20 21 /* 22 * Disable DM_* for SPL build and can be re-enabled after adding 23 * DM support in SPL 24 */ 25 #ifdef CONFIG_SPL_BUILD 26 #undef CONFIG_DM_SPI 27 #undef CONFIG_DM_SPI_FLASH 28 #undef CONFIG_DM_I2C 29 #undef CONFIG_DM_I2C_COMPAT 30 #endif 31 /* 32 * SoC Configuration 33 */ 34 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 35 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 36 #define CONFIG_SYS_OSCIN_FREQ 24000000 37 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 38 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 39 40 #ifdef CONFIG_DIRECT_NOR_BOOT 41 #define CONFIG_ARCH_CPU_INIT 42 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 43 #endif 44 45 /* 46 * Memory Info 47 */ 48 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 49 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 50 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 51 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 52 53 /* memtest start addr */ 54 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 55 56 /* memtest will be run on 16MB */ 57 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 58 59 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 60 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 61 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 62 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 63 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 64 DAVINCI_SYSCFG_SUSPSRC_I2C) 65 66 /* 67 * PLL configuration 68 */ 69 70 #define CONFIG_SYS_DA850_PLL0_PLLM 24 71 #define CONFIG_SYS_DA850_PLL1_PLLM 21 72 73 /* 74 * DDR2 memory configuration 75 */ 76 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 77 DV_DDR_PHY_EXT_STRBEN | \ 78 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 79 80 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 81 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 82 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 83 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 84 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 85 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 86 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 87 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 88 89 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 90 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 91 92 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 93 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 94 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 95 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 96 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 97 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 98 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 99 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 100 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 101 102 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 103 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 104 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 105 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 106 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 107 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 108 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 109 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 110 111 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 112 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 113 114 /* 115 * Serial Driver info 116 */ 117 118 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) 119 #define CONFIG_SYS_NS16550_SERIAL 120 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 121 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 122 #endif 123 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 124 125 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 128 #define CONFIG_SF_DEFAULT_SPEED 30000000 129 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 130 #endif 131 132 #ifdef CONFIG_USE_SPIFLASH 133 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 134 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 135 #endif 136 137 /* 138 * I2C Configuration 139 */ 140 #ifndef CONFIG_SPL_BUILD 141 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 142 #endif 143 144 /* 145 * Flash & Environment 146 */ 147 #ifdef CONFIG_NAND 148 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 149 #define CONFIG_ENV_SIZE (128 << 10) 150 #define CONFIG_SYS_NAND_USE_FLASH_BBT 151 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 152 #define CONFIG_SYS_NAND_PAGE_2K 153 #define CONFIG_SYS_NAND_CS 3 154 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 155 #define CONFIG_SYS_NAND_MASK_CLE 0x10 156 #define CONFIG_SYS_NAND_MASK_ALE 0x8 157 #undef CONFIG_SYS_NAND_HW_ECC 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 159 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 160 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 161 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 162 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 163 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 164 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 165 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 166 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 167 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 168 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 169 CONFIG_SYS_MALLOC_LEN - \ 170 GENERATED_GBL_DATA_SIZE) 171 #define CONFIG_SYS_NAND_ECCPOS { \ 172 24, 25, 26, 27, 28, \ 173 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 174 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 175 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 176 59, 60, 61, 62, 63 } 177 #define CONFIG_SYS_NAND_PAGE_COUNT 64 178 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 179 #define CONFIG_SYS_NAND_ECCSIZE 512 180 #define CONFIG_SYS_NAND_ECCBYTES 10 181 #define CONFIG_SYS_NAND_OOBSIZE 64 182 #define CONFIG_SPL_NAND_BASE 183 #define CONFIG_SPL_NAND_DRIVERS 184 #define CONFIG_SPL_NAND_ECC 185 #define CONFIG_SPL_NAND_LOAD 186 #endif 187 188 /* 189 * Network & Ethernet Configuration 190 */ 191 #ifdef CONFIG_DRIVER_TI_EMAC 192 #define CONFIG_BOOTP_DNS2 193 #define CONFIG_BOOTP_SEND_HOSTNAME 194 #define CONFIG_NET_RETRY_COUNT 10 195 #endif 196 197 #ifdef CONFIG_USE_NOR 198 #define CONFIG_FLASH_CFI_DRIVER 199 #define CONFIG_SYS_FLASH_CFI 200 #define CONFIG_SYS_FLASH_PROTECTION 201 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 202 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 203 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 204 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 205 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 206 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 207 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 208 + 3) 209 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 210 #endif 211 212 #ifdef CONFIG_USE_SPIFLASH 213 #define CONFIG_ENV_SIZE (64 << 10) 214 #define CONFIG_ENV_OFFSET (512 << 10) 215 #define CONFIG_ENV_SECT_SIZE (64 << 10) 216 #ifdef CONFIG_SPL_BUILD 217 #undef CONFIG_SPI_FLASH_MTD 218 #endif 219 #endif 220 221 /* 222 * U-Boot general configuration 223 */ 224 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 225 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 226 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 227 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 228 #define CONFIG_MX_CYCLIC 229 230 /* 231 * Linux Information 232 */ 233 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 234 #define CONFIG_HWCONFIG /* enable hwconfig */ 235 #define CONFIG_CMDLINE_TAG 236 #define CONFIG_REVISION_TAG 237 #define CONFIG_SETUP_MEMORY_TAGS 238 239 #define CONFIG_BOOTCOMMAND \ 240 "run envboot; " \ 241 "run mmcboot; " 242 243 #define DEFAULT_LINUX_BOOT_ENV \ 244 "loadaddr=0xc0700000\0" \ 245 "fdtaddr=0xc0600000\0" \ 246 "scriptaddr=0xc0600000\0" 247 248 #include <environment/ti/mmc.h> 249 250 #define CONFIG_EXTRA_ENV_SETTINGS \ 251 DEFAULT_LINUX_BOOT_ENV \ 252 DEFAULT_MMC_TI_ARGS \ 253 "bootpart=0:2\0" \ 254 "bootdir=/boot\0" \ 255 "bootfile=zImage\0" \ 256 "fdtfile=da850-evm.dtb\0" \ 257 "boot_fdt=yes\0" \ 258 "boot_fit=0\0" \ 259 "console=ttyS2,115200n8\0" \ 260 "hwconfig=dsp:wake=yes" 261 262 #ifdef CONFIG_CMD_BDI 263 #define CONFIG_CLOCKS 264 #endif 265 266 #if !defined(CONFIG_NAND) && \ 267 !defined(CONFIG_USE_NOR) && \ 268 !defined(CONFIG_USE_SPIFLASH) 269 #define CONFIG_ENV_SIZE (16 << 10) 270 #endif 271 272 #ifndef CONFIG_DIRECT_NOR_BOOT 273 /* defines for SPL */ 274 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 275 CONFIG_SYS_MALLOC_LEN) 276 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 277 #define CONFIG_SPL_STACK 0x8001ff00 278 #define CONFIG_SPL_TEXT_BASE 0x80000000 279 #define CONFIG_SPL_MAX_FOOTPRINT 32768 280 #define CONFIG_SPL_PAD_TO 32768 281 #endif 282 283 /* Load U-Boot Image From MMC */ 284 285 /* additions for new relocation code, must added to all boards */ 286 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 287 288 #ifdef CONFIG_DIRECT_NOR_BOOT 289 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 290 #else 291 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 292 GENERATED_GBL_DATA_SIZE) 293 #endif /* CONFIG_DIRECT_NOR_BOOT */ 294 295 #include <asm/arch/hardware.h> 296 297 #endif /* __CONFIG_H */ 298