1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 /* 24 * Disable DM_* for SPL build and can be re-enabled after adding 25 * DM support in SPL 26 */ 27 #ifdef CONFIG_SPL_BUILD 28 #undef CONFIG_DM_SPI 29 #undef CONFIG_DM_SPI_FLASH 30 #undef CONFIG_DM_I2C 31 #undef CONFIG_DM_I2C_COMPAT 32 #endif 33 /* 34 * SoC Configuration 35 */ 36 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 37 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 38 #define CONFIG_SYS_OSCIN_FREQ 24000000 39 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 40 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 41 42 #ifdef CONFIG_DIRECT_NOR_BOOT 43 #define CONFIG_ARCH_CPU_INIT 44 #define CONFIG_DA8XX_GPIO 45 #define CONFIG_SYS_TEXT_BASE 0x60000000 46 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 47 #else 48 #define CONFIG_SYS_TEXT_BASE 0xc1080000 49 #endif 50 51 /* 52 * Memory Info 53 */ 54 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 55 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 56 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 57 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 58 59 /* memtest start addr */ 60 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 61 62 /* memtest will be run on 16MB */ 63 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 64 65 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 66 67 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 68 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 69 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 70 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 71 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 72 DAVINCI_SYSCFG_SUSPSRC_I2C) 73 74 /* 75 * PLL configuration 76 */ 77 #define CONFIG_SYS_DV_CLKMODE 0 78 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 79 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 80 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 81 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 82 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 83 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 84 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 85 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 86 87 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 88 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 89 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 90 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 91 92 #define CONFIG_SYS_DA850_PLL0_PLLM 24 93 #define CONFIG_SYS_DA850_PLL1_PLLM 21 94 95 /* 96 * DDR2 memory configuration 97 */ 98 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 99 DV_DDR_PHY_EXT_STRBEN | \ 100 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 101 102 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 103 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 104 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 105 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 106 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 107 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 108 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 109 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 110 111 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 112 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 113 114 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 115 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 116 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 117 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 118 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 119 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 120 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 121 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 122 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 123 124 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 125 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 126 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 127 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 128 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 129 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 130 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 131 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 132 133 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 134 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 135 136 /* 137 * Serial Driver info 138 */ 139 140 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) 141 #define CONFIG_SYS_NS16550_SERIAL 142 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 143 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 144 #endif 145 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 146 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 147 148 #define CONFIG_SPI 149 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 150 #ifdef CONFIG_SPL_BUILD 151 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 152 #define CONFIG_SF_DEFAULT_SPEED 30000000 153 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 154 #endif 155 156 #ifdef CONFIG_USE_SPIFLASH 157 #define CONFIG_SPL_SPI_LOAD 158 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 159 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 160 #endif 161 162 /* 163 * I2C Configuration 164 */ 165 #ifndef CONFIG_SPL_BUILD 166 #define CONFIG_SYS_I2C_DAVINCI 167 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 168 #endif 169 170 /* 171 * Flash & Environment 172 */ 173 #ifdef CONFIG_USE_NAND 174 #define CONFIG_NAND_DAVINCI 175 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 176 #define CONFIG_ENV_SIZE (128 << 10) 177 #define CONFIG_SYS_NAND_USE_FLASH_BBT 178 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 179 #define CONFIG_SYS_NAND_PAGE_2K 180 #define CONFIG_SYS_NAND_CS 3 181 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 182 #define CONFIG_SYS_NAND_MASK_CLE 0x10 183 #define CONFIG_SYS_NAND_MASK_ALE 0x8 184 #undef CONFIG_SYS_NAND_HW_ECC 185 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 186 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 187 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 188 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 189 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 190 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 191 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 192 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 193 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 194 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 195 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 196 CONFIG_SYS_MALLOC_LEN - \ 197 GENERATED_GBL_DATA_SIZE) 198 #define CONFIG_SYS_NAND_ECCPOS { \ 199 24, 25, 26, 27, 28, \ 200 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 201 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 202 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 203 59, 60, 61, 62, 63 } 204 #define CONFIG_SYS_NAND_PAGE_COUNT 64 205 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 206 #define CONFIG_SYS_NAND_ECCSIZE 512 207 #define CONFIG_SYS_NAND_ECCBYTES 10 208 #define CONFIG_SYS_NAND_OOBSIZE 64 209 #define CONFIG_SPL_NAND_BASE 210 #define CONFIG_SPL_NAND_DRIVERS 211 #define CONFIG_SPL_NAND_ECC 212 #define CONFIG_SPL_NAND_LOAD 213 #endif 214 215 /* 216 * Network & Ethernet Configuration 217 */ 218 #ifdef CONFIG_DRIVER_TI_EMAC 219 #define CONFIG_MII 220 #define CONFIG_BOOTP_DNS 221 #define CONFIG_BOOTP_DNS2 222 #define CONFIG_BOOTP_SEND_HOSTNAME 223 #define CONFIG_NET_RETRY_COUNT 10 224 #endif 225 226 #ifdef CONFIG_USE_NOR 227 #define CONFIG_FLASH_CFI_DRIVER 228 #define CONFIG_SYS_FLASH_CFI 229 #define CONFIG_SYS_FLASH_PROTECTION 230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 231 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 232 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 233 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 234 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 235 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 236 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 237 + 3) 238 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 239 #endif 240 241 #ifdef CONFIG_USE_SPIFLASH 242 #define CONFIG_ENV_SIZE (64 << 10) 243 #define CONFIG_ENV_OFFSET (512 << 10) 244 #define CONFIG_ENV_SECT_SIZE (64 << 10) 245 #ifdef CONFIG_SPL_BUILD 246 #undef CONFIG_SPI_FLASH_MTD 247 #endif 248 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 249 #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ 250 #endif 251 252 /* 253 * U-Boot general configuration 254 */ 255 #define CONFIG_MISC_INIT_R 256 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 257 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 258 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 259 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 260 #define CONFIG_AUTO_COMPLETE 261 #define CONFIG_CMDLINE_EDITING 262 #define CONFIG_SYS_LONGHELP 263 #define CONFIG_MX_CYCLIC 264 265 /* 266 * Linux Information 267 */ 268 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 269 #define CONFIG_HWCONFIG /* enable hwconfig */ 270 #define CONFIG_CMDLINE_TAG 271 #define CONFIG_REVISION_TAG 272 #define CONFIG_SETUP_MEMORY_TAGS 273 274 #define CONFIG_BOOTCOMMAND \ 275 "run envboot; " \ 276 "run mmcboot; " 277 278 #define DEFAULT_LINUX_BOOT_ENV \ 279 "loadaddr=0xc0700000\0" \ 280 "fdtaddr=0xc0600000\0" \ 281 "scriptaddr=0xc0600000\0" 282 283 #include <environment/ti/mmc.h> 284 285 #define CONFIG_EXTRA_ENV_SETTINGS \ 286 DEFAULT_LINUX_BOOT_ENV \ 287 DEFAULT_MMC_TI_ARGS \ 288 "bootpart=0:2\0" \ 289 "bootdir=/boot\0" \ 290 "bootfile=zImage\0" \ 291 "fdtfile=da850-evm.dtb\0" \ 292 "boot_fdt=yes\0" \ 293 "boot_fit=0\0" \ 294 "console=ttyS2,115200n8\0" \ 295 "hwconfig=dsp:wake=yes" 296 297 #ifdef CONFIG_CMD_BDI 298 #define CONFIG_CLOCKS 299 #endif 300 301 #ifdef CONFIG_USE_NAND 302 #define CONFIG_MTD_DEVICE 303 #define CONFIG_MTD_PARTITIONS 304 #endif 305 306 #if !defined(CONFIG_USE_NAND) && \ 307 !defined(CONFIG_USE_NOR) && \ 308 !defined(CONFIG_USE_SPIFLASH) 309 #define CONFIG_ENV_SIZE (16 << 10) 310 #endif 311 312 #ifndef CONFIG_DIRECT_NOR_BOOT 313 /* defines for SPL */ 314 #define CONFIG_SPL_FRAMEWORK 315 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 316 CONFIG_SYS_MALLOC_LEN) 317 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 318 #define CONFIG_SPL_SPI_LOAD 319 #define CONFIG_SPL_STACK 0x8001ff00 320 #define CONFIG_SPL_TEXT_BASE 0x80000000 321 #define CONFIG_SPL_MAX_FOOTPRINT 32768 322 #define CONFIG_SPL_PAD_TO 32768 323 #endif 324 325 /* Load U-Boot Image From MMC */ 326 #ifdef CONFIG_SPL_MMC_LOAD 327 #undef CONFIG_SPL_SPI_LOAD 328 #endif 329 330 /* additions for new relocation code, must added to all boards */ 331 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 332 333 #ifdef CONFIG_DIRECT_NOR_BOOT 334 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 335 #else 336 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 337 GENERATED_GBL_DATA_SIZE) 338 #endif /* CONFIG_DIRECT_NOR_BOOT */ 339 340 #include <asm/arch/hardware.h> 341 342 #endif /* __CONFIG_H */ 343