1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 24 /* 25 * SoC Configuration 26 */ 27 #define CONFIG_MACH_DAVINCI_DA850_EVM 28 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 29 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 30 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 31 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 32 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 33 #define CONFIG_SYS_OSCIN_FREQ 24000000 34 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 35 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 36 #define CONFIG_SYS_HZ 1000 37 #define CONFIG_SYS_DA850_PLL_INIT 38 #define CONFIG_SYS_DA850_DDR_INIT 39 40 #ifdef CONFIG_DIRECT_NOR_BOOT 41 #define CONFIG_ARCH_CPU_INIT 42 #define CONFIG_DA8XX_GPIO 43 #define CONFIG_SYS_TEXT_BASE 0x60000000 44 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 45 #define CONFIG_DA850_LOWLEVEL 46 #else 47 #define CONFIG_SYS_TEXT_BASE 0xc1080000 48 #endif 49 50 /* 51 * Memory Info 52 */ 53 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 54 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 55 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 56 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 57 58 /* memtest start addr */ 59 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 60 61 /* memtest will be run on 16MB */ 62 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 63 64 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 65 66 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 67 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 68 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 69 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 70 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 71 DAVINCI_SYSCFG_SUSPSRC_I2C) 72 73 /* 74 * PLL configuration 75 */ 76 #define CONFIG_SYS_DV_CLKMODE 0 77 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 78 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 79 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 80 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 81 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 82 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 83 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 84 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 85 86 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 87 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 88 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 89 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 90 91 #define CONFIG_SYS_DA850_PLL0_PLLM 24 92 #define CONFIG_SYS_DA850_PLL1_PLLM 21 93 94 /* 95 * DDR2 memory configuration 96 */ 97 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 98 DV_DDR_PHY_EXT_STRBEN | \ 99 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 100 101 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 102 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 103 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 104 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 105 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 106 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 107 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 108 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 109 110 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 111 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 112 113 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 114 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 115 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 116 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 117 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 118 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 119 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 120 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 121 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 122 123 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 124 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 125 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 126 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 127 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 128 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 129 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 130 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 131 132 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 133 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 134 135 /* 136 * Serial Driver info 137 */ 138 #define CONFIG_SYS_NS16550 139 #define CONFIG_SYS_NS16550_SERIAL 140 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 141 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 142 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 143 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 144 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 145 146 #define CONFIG_SPI 147 #define CONFIG_SPI_FLASH 148 #define CONFIG_SPI_FLASH_STMICRO 149 #define CONFIG_SPI_FLASH_WINBOND 150 #define CONFIG_CMD_SF 151 #define CONFIG_DAVINCI_SPI 152 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 153 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 154 #define CONFIG_SF_DEFAULT_SPEED 30000000 155 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 156 157 #ifdef CONFIG_USE_SPIFLASH 158 #define CONFIG_SPL_SPI_SUPPORT 159 #define CONFIG_SPL_SPI_FLASH_SUPPORT 160 #define CONFIG_SPL_SPI_LOAD 161 #define CONFIG_SPL_SPI_BUS 0 162 #define CONFIG_SPL_SPI_CS 0 163 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 164 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 165 #endif 166 167 /* 168 * I2C Configuration 169 */ 170 #define CONFIG_HARD_I2C 171 #define CONFIG_DRIVER_DAVINCI_I2C 172 #define CONFIG_SYS_I2C_SPEED 25000 173 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 174 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 175 176 /* 177 * Flash & Environment 178 */ 179 #ifdef CONFIG_USE_NAND 180 #undef CONFIG_ENV_IS_IN_FLASH 181 #define CONFIG_NAND_DAVINCI 182 #define CONFIG_SYS_NO_FLASH 183 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 184 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 185 #define CONFIG_ENV_SIZE (128 << 10) 186 #define CONFIG_SYS_NAND_USE_FLASH_BBT 187 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 188 #define CONFIG_SYS_NAND_PAGE_2K 189 #define CONFIG_SYS_NAND_CS 3 190 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 191 #define CONFIG_SYS_NAND_MASK_CLE 0x10 192 #define CONFIG_SYS_NAND_MASK_ALE 0x8 193 #undef CONFIG_SYS_NAND_HW_ECC 194 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 195 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 196 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 197 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 198 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 199 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 200 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 201 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 202 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 203 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 204 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 205 CONFIG_SYS_MALLOC_LEN - \ 206 GENERATED_GBL_DATA_SIZE) 207 #define CONFIG_SYS_NAND_ECCPOS { \ 208 24, 25, 26, 27, 28, \ 209 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 210 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 211 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 212 59, 60, 61, 62, 63 } 213 #define CONFIG_SYS_NAND_PAGE_COUNT 64 214 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 215 #define CONFIG_SYS_NAND_ECCSIZE 512 216 #define CONFIG_SYS_NAND_ECCBYTES 10 217 #define CONFIG_SYS_NAND_OOBSIZE 64 218 #define CONFIG_SPL_NAND_SUPPORT 219 #define CONFIG_SPL_NAND_BASE 220 #define CONFIG_SPL_NAND_DRIVERS 221 #define CONFIG_SPL_NAND_ECC 222 #define CONFIG_SPL_NAND_SIMPLE 223 #define CONFIG_SPL_NAND_LOAD 224 #endif 225 226 /* 227 * Network & Ethernet Configuration 228 */ 229 #ifdef CONFIG_DRIVER_TI_EMAC 230 #define CONFIG_MII 231 #define CONFIG_BOOTP_DNS 232 #define CONFIG_BOOTP_DNS2 233 #define CONFIG_BOOTP_SEND_HOSTNAME 234 #define CONFIG_NET_RETRY_COUNT 10 235 #endif 236 237 #ifdef CONFIG_USE_NOR 238 #define CONFIG_ENV_IS_IN_FLASH 239 #define CONFIG_FLASH_CFI_DRIVER 240 #define CONFIG_SYS_FLASH_CFI 241 #define CONFIG_SYS_FLASH_PROTECTION 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 243 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 244 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 245 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 246 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 247 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 248 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 249 + 3) 250 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 251 #endif 252 253 #ifdef CONFIG_USE_SPIFLASH 254 #undef CONFIG_ENV_IS_IN_FLASH 255 #undef CONFIG_ENV_IS_IN_NAND 256 #define CONFIG_ENV_IS_IN_SPI_FLASH 257 #define CONFIG_ENV_SIZE (64 << 10) 258 #define CONFIG_ENV_OFFSET (256 << 10) 259 #define CONFIG_ENV_SECT_SIZE (64 << 10) 260 #define CONFIG_SYS_NO_FLASH 261 #endif 262 263 /* 264 * U-Boot general configuration 265 */ 266 #define CONFIG_MISC_INIT_R 267 #define CONFIG_BOARD_EARLY_INIT_F 268 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 269 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ 270 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 272 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 273 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 274 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 275 #define CONFIG_VERSION_VARIABLE 276 #define CONFIG_AUTO_COMPLETE 277 #define CONFIG_SYS_HUSH_PARSER 278 #define CONFIG_CMDLINE_EDITING 279 #define CONFIG_SYS_LONGHELP 280 #define CONFIG_CRC32_VERIFY 281 #define CONFIG_MX_CYCLIC 282 283 /* 284 * Linux Information 285 */ 286 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 287 #define CONFIG_HWCONFIG /* enable hwconfig */ 288 #define CONFIG_CMDLINE_TAG 289 #define CONFIG_REVISION_TAG 290 #define CONFIG_SETUP_MEMORY_TAGS 291 #define CONFIG_BOOTARGS \ 292 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" 293 #define CONFIG_BOOTDELAY 3 294 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" 295 296 /* 297 * U-Boot commands 298 */ 299 #include <config_cmd_default.h> 300 #define CONFIG_CMD_ENV 301 #define CONFIG_CMD_ASKENV 302 #define CONFIG_CMD_DHCP 303 #define CONFIG_CMD_DIAG 304 #define CONFIG_CMD_MII 305 #define CONFIG_CMD_PING 306 #define CONFIG_CMD_SAVES 307 #define CONFIG_CMD_MEMORY 308 309 #ifdef CONFIG_CMD_BDI 310 #define CONFIG_CLOCKS 311 #endif 312 313 #ifndef CONFIG_DRIVER_TI_EMAC 314 #undef CONFIG_CMD_NET 315 #undef CONFIG_CMD_DHCP 316 #undef CONFIG_CMD_MII 317 #undef CONFIG_CMD_PING 318 #endif 319 320 #ifdef CONFIG_USE_NAND 321 #undef CONFIG_CMD_FLASH 322 #undef CONFIG_CMD_IMLS 323 #define CONFIG_CMD_NAND 324 325 #define CONFIG_CMD_MTDPARTS 326 #define CONFIG_MTD_DEVICE 327 #define CONFIG_MTD_PARTITIONS 328 #define CONFIG_LZO 329 #define CONFIG_RBTREE 330 #define CONFIG_CMD_UBI 331 #define CONFIG_CMD_UBIFS 332 #endif 333 334 #ifdef CONFIG_USE_SPIFLASH 335 #undef CONFIG_CMD_IMLS 336 #undef CONFIG_CMD_FLASH 337 #define CONFIG_CMD_SPI 338 #define CONFIG_CMD_SAVEENV 339 #endif 340 341 #if !defined(CONFIG_USE_NAND) && \ 342 !defined(CONFIG_USE_NOR) && \ 343 !defined(CONFIG_USE_SPIFLASH) 344 #define CONFIG_ENV_IS_NOWHERE 345 #define CONFIG_SYS_NO_FLASH 346 #define CONFIG_ENV_SIZE (16 << 10) 347 #undef CONFIG_CMD_IMLS 348 #undef CONFIG_CMD_ENV 349 #endif 350 351 /* SD/MMC configuration */ 352 #ifndef CONFIG_USE_NOR 353 #define CONFIG_MMC 354 #define CONFIG_DAVINCI_MMC_SD1 355 #define CONFIG_GENERIC_MMC 356 #define CONFIG_DAVINCI_MMC 357 #endif 358 359 /* 360 * Enable MMC commands only when 361 * MMC support is present 362 */ 363 #ifdef CONFIG_MMC 364 #define CONFIG_DOS_PARTITION 365 #define CONFIG_CMD_EXT2 366 #define CONFIG_CMD_FAT 367 #define CONFIG_CMD_MMC 368 #endif 369 370 #ifndef CONFIG_DIRECT_NOR_BOOT 371 /* defines for SPL */ 372 #define CONFIG_SPL 373 #define CONFIG_SPL_FRAMEWORK 374 #define CONFIG_SPL_BOARD_INIT 375 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 376 CONFIG_SYS_MALLOC_LEN) 377 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 378 #define CONFIG_SPL_SPI_SUPPORT 379 #define CONFIG_SPL_SPI_FLASH_SUPPORT 380 #define CONFIG_SPL_SPI_LOAD 381 #define CONFIG_SPL_SPI_BUS 0 382 #define CONFIG_SPL_SPI_CS 0 383 #define CONFIG_SPL_SERIAL_SUPPORT 384 #define CONFIG_SPL_LIBCOMMON_SUPPORT 385 #define CONFIG_SPL_LIBGENERIC_SUPPORT 386 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" 387 #define CONFIG_SPL_STACK 0x8001ff00 388 #define CONFIG_SPL_TEXT_BASE 0x80000000 389 #define CONFIG_SPL_MAX_FOOTPRINT 32768 390 #endif 391 392 /* Load U-Boot Image From MMC */ 393 #ifdef CONFIG_SPL_MMC_LOAD 394 #define CONFIG_SPL_MMC_SUPPORT 395 #define CONFIG_SPL_LIBDISK_SUPPORT 396 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 397 #undef CONFIG_SPL_SPI_SUPPORT 398 #undef CONFIG_SPL_SPI_LOAD 399 #endif 400 401 /* additions for new relocation code, must added to all boards */ 402 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 403 404 #ifdef CONFIG_DIRECT_NOR_BOOT 405 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 406 #else 407 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 408 GENERATED_GBL_DATA_SIZE) 409 #endif /* CONFIG_DIRECT_NOR_BOOT */ 410 #endif /* __CONFIG_H */ 411