1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * Board 28 */ 29 #define CONFIG_DRIVER_TI_EMAC 30 #define CONFIG_USE_SPIFLASH 31 32 33 /* 34 * SoC Configuration 35 */ 36 #define CONFIG_MACH_DAVINCI_DA850_EVM 37 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 38 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 39 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 40 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 41 #define CONFIG_SYS_OSCIN_FREQ 24000000 42 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 43 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 44 #define CONFIG_SYS_HZ 1000 45 #define CONFIG_SKIP_LOWLEVEL_INIT 46 #define CONFIG_SYS_TEXT_BASE 0xc1080000 47 #define CONFIG_SYS_ICACHE_OFF 48 #define CONFIG_SYS_DCACHE_OFF 49 #define CONFIG_SYS_L2CACHE_OFF 50 51 /* 52 * Memory Info 53 */ 54 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 55 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 56 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 57 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 58 59 /* memtest start addr */ 60 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 61 62 /* memtest will be run on 16MB */ 63 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 64 65 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 66 #define CONFIG_STACKSIZE (256*1024) /* regular stack */ 67 68 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 69 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 70 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 71 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 72 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 73 DAVINCI_SYSCFG_SUSPSRC_I2C) 74 75 /* 76 * PLL configuration 77 */ 78 #define CONFIG_SYS_DV_CLKMODE 0 79 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 80 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 81 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 82 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 83 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 84 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 85 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 86 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 87 88 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 89 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 90 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 91 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 92 93 #define CONFIG_SYS_DA850_PLL0_PLLM 24 94 #define CONFIG_SYS_DA850_PLL1_PLLM 21 95 96 /* 97 * DDR2 memory configuration 98 */ 99 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 100 DV_DDR_PHY_EXT_STRBEN | \ 101 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 102 103 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 104 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 105 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 106 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 107 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 108 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 109 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 110 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 111 112 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 113 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 114 115 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 116 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 117 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 118 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 119 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 120 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 121 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 122 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 123 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 124 125 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 126 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 127 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 128 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 129 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 130 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 131 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 132 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 133 134 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 135 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 136 137 /* 138 * Serial Driver info 139 */ 140 #define CONFIG_SYS_NS16550 141 #define CONFIG_SYS_NS16550_SERIAL 142 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 143 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 144 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 145 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 146 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 147 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 148 #define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 149 150 #define CONFIG_SPI 151 #define CONFIG_SPI_FLASH 152 #define CONFIG_SPI_FLASH_STMICRO 153 #define CONFIG_SPI_FLASH_WINBOND 154 #define CONFIG_DAVINCI_SPI 155 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 156 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 157 #define CONFIG_SF_DEFAULT_SPEED 30000000 158 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 159 160 /* 161 * I2C Configuration 162 */ 163 #define CONFIG_HARD_I2C 164 #define CONFIG_DRIVER_DAVINCI_I2C 165 #define CONFIG_SYS_I2C_SPEED 25000 166 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 167 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 168 169 /* 170 * Flash & Environment 171 */ 172 #ifdef CONFIG_USE_NAND 173 #undef CONFIG_ENV_IS_IN_FLASH 174 #define CONFIG_NAND_DAVINCI 175 #define CONFIG_SYS_NO_FLASH 176 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 177 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 178 #define CONFIG_ENV_SIZE (128 << 10) 179 #define CONFIG_SYS_NAND_USE_FLASH_BBT 180 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 181 #define CONFIG_SYS_NAND_PAGE_2K 182 #define CONFIG_SYS_NAND_CS 3 183 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 184 #define CONFIG_SYS_CLE_MASK 0x10 185 #define CONFIG_SYS_ALE_MASK 0x8 186 #undef CONFIG_SYS_NAND_HW_ECC 187 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 188 #define NAND_MAX_CHIPS 1 189 #endif 190 191 /* 192 * Network & Ethernet Configuration 193 */ 194 #ifdef CONFIG_DRIVER_TI_EMAC 195 #define CONFIG_MII 196 #define CONFIG_BOOTP_DEFAULT 197 #define CONFIG_BOOTP_DNS 198 #define CONFIG_BOOTP_DNS2 199 #define CONFIG_BOOTP_SEND_HOSTNAME 200 #define CONFIG_NET_RETRY_COUNT 10 201 #endif 202 203 #ifdef CONFIG_USE_NOR 204 #define CONFIG_ENV_IS_IN_FLASH 205 #define CONFIG_FLASH_CFI_DRIVER 206 #define CONFIG_SYS_FLASH_CFI 207 #define CONFIG_SYS_FLASH_PROTECTION 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 209 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 210 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 211 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 212 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 213 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 214 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 215 + 3) 216 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 217 #endif 218 219 #ifdef CONFIG_USE_SPIFLASH 220 #undef CONFIG_ENV_IS_IN_FLASH 221 #undef CONFIG_ENV_IS_IN_NAND 222 #define CONFIG_ENV_IS_IN_SPI_FLASH 223 #define CONFIG_ENV_SIZE (64 << 10) 224 #define CONFIG_ENV_OFFSET (256 << 10) 225 #define CONFIG_ENV_SECT_SIZE (64 << 10) 226 #define CONFIG_SYS_NO_FLASH 227 #endif 228 229 /* 230 * U-Boot general configuration 231 */ 232 #define CONFIG_MISC_INIT_R 233 #define CONFIG_BOARD_EARLY_INIT_F 234 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 235 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ 236 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 237 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 238 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 239 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 240 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 241 #define CONFIG_VERSION_VARIABLE 242 #define CONFIG_AUTO_COMPLETE 243 #define CONFIG_SYS_HUSH_PARSER 244 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 245 #define CONFIG_CMDLINE_EDITING 246 #define CONFIG_SYS_LONGHELP 247 #define CONFIG_CRC32_VERIFY 248 #define CONFIG_MX_CYCLIC 249 250 /* 251 * Linux Information 252 */ 253 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 254 #define CONFIG_HWCONFIG /* enable hwconfig */ 255 #define CONFIG_CMDLINE_TAG 256 #define CONFIG_REVISION_TAG 257 #define CONFIG_SETUP_MEMORY_TAGS 258 #define CONFIG_BOOTARGS \ 259 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" 260 #define CONFIG_BOOTDELAY 3 261 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" 262 263 /* 264 * U-Boot commands 265 */ 266 #include <config_cmd_default.h> 267 #define CONFIG_CMD_ENV 268 #define CONFIG_CMD_ASKENV 269 #define CONFIG_CMD_DHCP 270 #define CONFIG_CMD_DIAG 271 #define CONFIG_CMD_MII 272 #define CONFIG_CMD_PING 273 #define CONFIG_CMD_SAVES 274 #define CONFIG_CMD_MEMORY 275 276 #ifndef CONFIG_DRIVER_TI_EMAC 277 #undef CONFIG_CMD_NET 278 #undef CONFIG_CMD_DHCP 279 #undef CONFIG_CMD_MII 280 #undef CONFIG_CMD_PING 281 #endif 282 283 #ifdef CONFIG_USE_NAND 284 #undef CONFIG_CMD_FLASH 285 #undef CONFIG_CMD_IMLS 286 #define CONFIG_CMD_NAND 287 288 #define CONFIG_CMD_MTDPARTS 289 #define CONFIG_MTD_DEVICE 290 #define CONFIG_MTD_PARTITIONS 291 #define CONFIG_LZO 292 #define CONFIG_RBTREE 293 #define CONFIG_CMD_UBI 294 #define CONFIG_CMD_UBIFS 295 #endif 296 297 #ifdef CONFIG_USE_SPIFLASH 298 #undef CONFIG_CMD_IMLS 299 #undef CONFIG_CMD_FLASH 300 #define CONFIG_CMD_SPI 301 #define CONFIG_CMD_SF 302 #define CONFIG_CMD_SAVEENV 303 #endif 304 305 #if !defined(CONFIG_USE_NAND) && \ 306 !defined(CONFIG_USE_NOR) && \ 307 !defined(CONFIG_USE_SPIFLASH) 308 #define CONFIG_ENV_IS_NOWHERE 309 #define CONFIG_SYS_NO_FLASH 310 #define CONFIG_ENV_SIZE (16 << 10) 311 #undef CONFIG_CMD_IMLS 312 #undef CONFIG_CMD_ENV 313 #endif 314 315 /* defines for SPL */ 316 #define CONFIG_SPL 317 #define CONFIG_SPL_SPI_SUPPORT 318 #define CONFIG_SPL_SPI_FLASH_SUPPORT 319 #define CONFIG_SPL_SPI_LOAD 320 #define CONFIG_SPL_SPI_BUS 0 321 #define CONFIG_SPL_SPI_CS 0 322 #define CONFIG_SPL_SERIAL_SUPPORT 323 #define CONFIG_SPL_LIBCOMMON_SUPPORT 324 #define CONFIG_SPL_LIBGENERIC_SUPPORT 325 #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" 326 #define CONFIG_SPL_STACK 0x8001ff00 327 #define CONFIG_SPL_TEXT_BASE 0x80000000 328 #define CONFIG_SPL_MAX_SIZE 32768 329 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 330 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 331 332 /* additions for new relocation code, must added to all boards */ 333 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 334 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 335 GENERATED_GBL_DATA_SIZE) 336 #endif /* __CONFIG_H */ 337