1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_MMC 17 #define CONFIG_SDCARD 18 #define CONFIG_FSL_SATA_V2 19 #define CONFIG_PCIE3 20 #define CONFIG_PCIE4 21 #ifdef CONFIG_ARCH_P5020 22 #define CONFIG_SYS_FSL_RAID_ENGINE 23 #define CONFIG_SYS_DPAA_RMAN 24 #endif 25 #define CONFIG_SYS_DPAA_PME 26 27 /* 28 * Corenet DS style board configuration file 29 */ 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 33 #if defined(CONFIG_ARCH_P5020) 34 #define CONFIG_SYS_CLK_FREQ 133000000 35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 36 #elif defined(CONFIG_ARCH_P5040) 37 #define CONFIG_SYS_CLK_FREQ 100000000 38 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_E500MC /* BOOKE e500mc family */ 45 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #define CONFIG_SYS_MMC_MAX_DEVICE 1 49 50 #ifndef CONFIG_SYS_TEXT_BASE 51 #define CONFIG_SYS_TEXT_BASE 0xeff40000 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 57 #define CONFIG_PCIE1 /* PCIE controller 1 */ 58 #define CONFIG_PCIE2 /* PCIE controller 2 */ 59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 61 62 #define CONFIG_ENV_OVERWRITE 63 64 #define CONFIG_SYS_NO_FLASH 65 66 #if defined(CONFIG_SDCARD) 67 #define CONFIG_SYS_EXTRA_ENV_RELOC 68 #define CONFIG_ENV_IS_IN_MMC 69 #define CONFIG_FSL_FIXED_MMC_LOCATION 70 #define CONFIG_SYS_MMC_ENV_DEV 0 71 #define CONFIG_ENV_SIZE 0x2000 72 #define CONFIG_ENV_OFFSET (512 * 1658) 73 #endif 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_SYS_CACHE_STASHING 79 #define CONFIG_BACKSIDE_L2_CACHE 80 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 81 #define CONFIG_BTB /* toggle branch predition */ 82 #define CONFIG_DDR_ECC 83 #ifdef CONFIG_DDR_ECC 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 85 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 86 #endif 87 88 #define CONFIG_ENABLE_36BIT_PHYS 89 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_ADDR_MAP 92 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 93 #endif 94 95 /* test POST memory test */ 96 #undef CONFIG_POST 97 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 98 #define CONFIG_SYS_MEMTEST_END 0x00400000 99 #define CONFIG_SYS_ALT_MEMTEST 100 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 101 102 /* 103 * Config the L3 Cache as L3 SRAM 104 */ 105 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 106 #ifdef CONFIG_PHYS_64BIT 107 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 108 #else 109 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 110 #endif 111 #define CONFIG_SYS_L3_SIZE (1024 << 10) 112 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 113 114 #ifdef CONFIG_PHYS_64BIT 115 #define CONFIG_SYS_DCSRBAR 0xf0000000 116 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 117 #endif 118 119 /* 120 * DDR Setup 121 */ 122 #define CONFIG_VERY_BIG_RAM 123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 125 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 128 129 #define CONFIG_DDR_SPD 130 #define CONFIG_SYS_FSL_DDR3 131 132 #define CONFIG_SYS_SPD_BUS_NUM 1 133 #define SPD_EEPROM_ADDRESS1 0x51 134 #define SPD_EEPROM_ADDRESS2 0x52 135 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 136 137 /* 138 * Local Bus Definitions 139 */ 140 141 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 144 #else 145 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 146 #endif 147 148 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 151 #else 152 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 153 #endif 154 155 /* Set the local bus clock 1/16 of platform clock */ 156 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 157 158 #define CONFIG_SYS_BR0_PRELIM \ 159 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 160 #define CONFIG_SYS_BR1_PRELIM \ 161 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 162 163 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 164 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 165 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 167 168 #if defined(CONFIG_RAMBOOT_PBL) 169 #define CONFIG_SYS_RAMBOOT 170 #endif 171 172 #define CONFIG_BOARD_EARLY_INIT_F 173 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 174 #define CONFIG_MISC_INIT_R 175 176 #define CONFIG_HWCONFIG 177 178 /* define to use L1 as initial stack */ 179 #define CONFIG_L1_INIT_RAM 180 #define CONFIG_SYS_INIT_RAM_LOCK 181 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 185 /* The assembler doesn't like typecast */ 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 187 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 188 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 189 #else 190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 193 #endif 194 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 195 196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 197 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 198 199 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 200 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 201 202 /* Serial Port - controlled on board with jumper J8 203 * open - index 2 204 * shorted - index 1 205 */ 206 #define CONFIG_CONS_INDEX 1 207 #define CONFIG_SYS_NS16550_SERIAL 208 #define CONFIG_SYS_NS16550_REG_SIZE 1 209 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 210 211 #define CONFIG_SYS_BAUDRATE_TABLE \ 212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 213 214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 216 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 217 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 218 219 /* I2C */ 220 #define CONFIG_SYS_I2C 221 #define CONFIG_SYS_I2C_FSL 222 #define CONFIG_I2C_MULTI_BUS 223 #define CONFIG_I2C_CMD_TREE 224 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 225 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 227 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 228 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 229 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 230 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 231 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 232 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 233 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 234 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 235 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 236 237 #define CONFIG_ID_EEPROM 238 #define CONFIG_SYS_I2C_EEPROM_NXID 239 #define CONFIG_SYS_EEPROM_BUS_NUM 0 240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 242 243 #define CONFIG_SYS_I2C_GENERIC_MAC 244 #define CONFIG_SYS_I2C_MAC1_BUS 3 245 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 246 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 247 #define CONFIG_SYS_I2C_MAC2_BUS 0 248 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 249 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 250 251 #define CONFIG_CMD_DATE 1 252 #define CONFIG_RTC_MCP79411 1 253 #define CONFIG_SYS_RTC_BUS_NUM 3 254 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 255 256 /* 257 * eSPI - Enhanced SPI 258 */ 259 260 /* 261 * General PCI 262 * Memory space is mapped 1-1, but I/O space must start from 0. 263 */ 264 265 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 266 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 267 #ifdef CONFIG_PHYS_64BIT 268 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 269 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 270 #else 271 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 272 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 273 #endif 274 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 275 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 276 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 279 #else 280 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 281 #endif 282 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 283 284 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 285 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 288 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 289 #else 290 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 291 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 292 #endif 293 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 294 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 295 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 296 #ifdef CONFIG_PHYS_64BIT 297 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 298 #else 299 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 300 #endif 301 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 302 303 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 304 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 305 #ifdef CONFIG_PHYS_64BIT 306 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 307 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 308 #else 309 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 310 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 311 #endif 312 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 313 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 314 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 315 #ifdef CONFIG_PHYS_64BIT 316 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 317 #else 318 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 319 #endif 320 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 321 322 /* controller 4, Base address 203000 */ 323 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 324 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 325 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 326 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 327 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 328 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 329 330 /* Qman/Bman */ 331 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 332 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 333 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 336 #else 337 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 338 #endif 339 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 340 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 341 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 342 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 343 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 344 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 345 CONFIG_SYS_BMAN_CENA_SIZE) 346 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 347 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 348 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 349 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 352 #else 353 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 354 #endif 355 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 356 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 357 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 358 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 359 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 360 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 361 CONFIG_SYS_QMAN_CENA_SIZE) 362 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 363 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 364 365 #define CONFIG_SYS_DPAA_FMAN 366 /* Default address of microcode for the Linux Fman driver */ 367 /* 368 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 369 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 370 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 371 */ 372 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 373 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 374 375 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 376 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 377 378 #ifdef CONFIG_SYS_DPAA_FMAN 379 #define CONFIG_FMAN_ENET 380 #define CONFIG_PHY_MICREL 381 #define CONFIG_PHY_MICREL_KSZ9021 382 #endif 383 384 #ifdef CONFIG_PCI 385 #define CONFIG_PCI_INDIRECT_BRIDGE 386 #define CONFIG_NET_MULTI 387 388 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 389 #define CONFIG_DOS_PARTITION 390 #endif /* CONFIG_PCI */ 391 392 /* SATA */ 393 #ifdef CONFIG_FSL_SATA_V2 394 #define CONFIG_LIBATA 395 #define CONFIG_FSL_SATA 396 397 #define CONFIG_SYS_SATA_MAX_DEVICE 2 398 #define CONFIG_SATA1 399 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 400 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 401 #define CONFIG_SATA2 402 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 403 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 404 405 #define CONFIG_LBA48 406 #define CONFIG_CMD_SATA 407 #define CONFIG_DOS_PARTITION 408 #endif 409 410 #ifdef CONFIG_FMAN_ENET 411 #define CONFIG_SYS_TBIPA_VALUE 8 412 #define CONFIG_MII /* MII PHY management */ 413 #define CONFIG_ETHPRIME "FM1@DTSEC4" 414 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 415 #endif 416 417 /* 418 * Environment 419 */ 420 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 421 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 422 423 /* 424 * Command line configuration. 425 */ 426 #define CONFIG_CMD_ERRATA 427 #define CONFIG_CMD_IRQ 428 #define CONFIG_CMD_REGINFO 429 430 #ifdef CONFIG_PCI 431 #define CONFIG_CMD_PCI 432 #endif 433 434 /* 435 * USB 436 */ 437 #define CONFIG_HAS_FSL_DR_USB 438 #define CONFIG_HAS_FSL_MPH_USB 439 440 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 441 #define CONFIG_USB_EHCI 442 #define CONFIG_USB_EHCI_FSL 443 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 444 #define CONFIG_EHCI_IS_TDI 445 #define CONFIG_SYS_USB_EVENT_POLL 446 /* _VIA_CONTROL_EP */ 447 #endif 448 449 #ifdef CONFIG_MMC 450 #define CONFIG_FSL_ESDHC 451 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 452 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 453 #define CONFIG_GENERIC_MMC 454 #define CONFIG_DOS_PARTITION 455 #endif 456 457 /* 458 * Miscellaneous configurable options 459 */ 460 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 461 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 462 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 463 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 464 #ifdef CONFIG_CMD_KGDB 465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 466 #else 467 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 468 #endif 469 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 470 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 471 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 472 473 /* 474 * For booting Linux, the board info and command line data 475 * have to be in the first 64 MB of memory, since this is 476 * the maximum mapped by the Linux kernel during initialization. 477 */ 478 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 479 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 480 481 #ifdef CONFIG_CMD_KGDB 482 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 483 #endif 484 485 /* 486 * Environment Configuration 487 */ 488 #define CONFIG_ROOTPATH "/opt/nfsroot" 489 #define CONFIG_BOOTFILE "uImage" 490 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 491 492 /* default location for tftp and bootm */ 493 #define CONFIG_LOADADDR 1000000 494 495 496 #define CONFIG_BAUDRATE 115200 497 498 #define __USB_PHY_TYPE utmi 499 500 #define CONFIG_EXTRA_ENV_SETTINGS \ 501 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 502 "bank_intlv=cs0_cs1;" \ 503 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 504 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 505 "netdev=eth0\0" \ 506 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 507 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 508 "consoledev=ttyS0\0" \ 509 "ramdiskaddr=2000000\0" \ 510 "fdtaddr=1e00000\0" \ 511 "bdev=sda3\0" 512 513 #define CONFIG_HDBOOT \ 514 "setenv bootargs root=/dev/$bdev rw " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $loadaddr $bootfile;" \ 517 "tftp $fdtaddr $fdtfile;" \ 518 "bootm $loadaddr - $fdtaddr" 519 520 #define CONFIG_NFSBOOTCOMMAND \ 521 "setenv bootargs root=/dev/nfs rw " \ 522 "nfsroot=$serverip:$rootpath " \ 523 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "tftp $loadaddr $bootfile;" \ 526 "tftp $fdtaddr $fdtfile;" \ 527 "bootm $loadaddr - $fdtaddr" 528 529 #define CONFIG_RAMBOOTCOMMAND \ 530 "setenv bootargs root=/dev/ram rw " \ 531 "console=$consoledev,$baudrate $othbootargs;" \ 532 "tftp $ramdiskaddr $ramdiskfile;" \ 533 "tftp $loadaddr $bootfile;" \ 534 "tftp $fdtaddr $fdtfile;" \ 535 "bootm $loadaddr $ramdiskaddr $fdtaddr" 536 537 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 538 539 #include <asm/fsl_secure_boot.h> 540 541 #ifdef CONFIG_SECURE_BOOT 542 #endif 543 544 #endif /* __CONFIG_H */ 545