1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Based on corenet_ds.h 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 10 #error Must call Cyrus CONFIG with a specific CPU enabled. 11 #endif 12 13 #define CONFIG_SDCARD 14 #define CONFIG_FSL_SATA_V2 15 #define CONFIG_PCIE3 16 #define CONFIG_PCIE4 17 #ifdef CONFIG_ARCH_P5020 18 #define CONFIG_SYS_FSL_RAID_ENGINE 19 #define CONFIG_SYS_DPAA_RMAN 20 #endif 21 #define CONFIG_SYS_DPAA_PME 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 29 #if defined(CONFIG_ARCH_P5020) 30 #define CONFIG_SYS_CLK_FREQ 133000000 31 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 32 #elif defined(CONFIG_ARCH_P5040) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 40 #define CONFIG_SYS_MMC_MAX_DEVICE 1 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 44 #define CONFIG_PCIE1 /* PCIE controller 1 */ 45 #define CONFIG_PCIE2 /* PCIE controller 2 */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #if defined(CONFIG_SDCARD) 52 #define CONFIG_FSL_FIXED_MMC_LOCATION 53 #define CONFIG_SYS_MMC_ENV_DEV 0 54 #define CONFIG_ENV_SIZE 0x2000 55 #define CONFIG_ENV_OFFSET (512 * 1658) 56 #endif 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_SYS_CACHE_STASHING 62 #define CONFIG_BACKSIDE_L2_CACHE 63 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 64 #define CONFIG_BTB /* toggle branch predition */ 65 #define CONFIG_DDR_ECC 66 #ifdef CONFIG_DDR_ECC 67 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 68 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 69 #endif 70 71 #define CONFIG_ENABLE_36BIT_PHYS 72 73 #ifdef CONFIG_PHYS_64BIT 74 #define CONFIG_ADDR_MAP 75 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 76 #endif 77 78 /* test POST memory test */ 79 #undef CONFIG_POST 80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 81 #define CONFIG_SYS_MEMTEST_END 0x00400000 82 83 /* 84 * Config the L3 Cache as L3 SRAM 85 */ 86 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 87 #ifdef CONFIG_PHYS_64BIT 88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 89 #else 90 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 91 #endif 92 #define CONFIG_SYS_L3_SIZE (1024 << 10) 93 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 94 95 #ifdef CONFIG_PHYS_64BIT 96 #define CONFIG_SYS_DCSRBAR 0xf0000000 97 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 98 #endif 99 100 /* 101 * DDR Setup 102 */ 103 #define CONFIG_VERY_BIG_RAM 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 109 110 #define CONFIG_DDR_SPD 111 112 #define CONFIG_SYS_SPD_BUS_NUM 1 113 #define SPD_EEPROM_ADDRESS1 0x51 114 #define SPD_EEPROM_ADDRESS2 0x52 115 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 116 117 /* 118 * Local Bus Definitions 119 */ 120 121 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 124 #else 125 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 126 #endif 127 128 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 131 #else 132 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 133 #endif 134 135 /* Set the local bus clock 1/16 of platform clock */ 136 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 137 138 #define CONFIG_SYS_BR0_PRELIM \ 139 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 140 #define CONFIG_SYS_BR1_PRELIM \ 141 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 142 143 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 144 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 145 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 147 148 #if defined(CONFIG_RAMBOOT_PBL) 149 #define CONFIG_SYS_RAMBOOT 150 #endif 151 152 #define CONFIG_HWCONFIG 153 154 /* define to use L1 as initial stack */ 155 #define CONFIG_L1_INIT_RAM 156 #define CONFIG_SYS_INIT_RAM_LOCK 157 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 158 #ifdef CONFIG_PHYS_64BIT 159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 161 /* The assembler doesn't like typecast */ 162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 163 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 164 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 165 #else 166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 169 #endif 170 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 171 172 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 174 175 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 176 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 177 178 /* Serial Port - controlled on board with jumper J8 179 * open - index 2 180 * shorted - index 1 181 */ 182 #define CONFIG_SYS_NS16550_SERIAL 183 #define CONFIG_SYS_NS16550_REG_SIZE 1 184 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 185 186 #define CONFIG_SYS_BAUDRATE_TABLE \ 187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 188 189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 191 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 192 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 193 194 /* I2C */ 195 #define CONFIG_SYS_I2C 196 #define CONFIG_SYS_I2C_FSL 197 #define CONFIG_I2C_MULTI_BUS 198 #define CONFIG_I2C_CMD_TREE 199 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 200 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 201 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 202 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 203 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 204 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 205 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 206 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 207 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 208 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 209 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 211 212 #define CONFIG_ID_EEPROM 213 #define CONFIG_SYS_I2C_EEPROM_NXID 214 #define CONFIG_SYS_EEPROM_BUS_NUM 0 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 217 218 #define CONFIG_SYS_I2C_GENERIC_MAC 219 #define CONFIG_SYS_I2C_MAC1_BUS 3 220 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 221 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 222 #define CONFIG_SYS_I2C_MAC2_BUS 0 223 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 224 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 225 226 #define CONFIG_RTC_MCP79411 1 227 #define CONFIG_SYS_RTC_BUS_NUM 3 228 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 229 230 /* 231 * eSPI - Enhanced SPI 232 */ 233 234 /* 235 * General PCI 236 * Memory space is mapped 1-1, but I/O space must start from 0. 237 */ 238 239 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 240 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 241 #ifdef CONFIG_PHYS_64BIT 242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 244 #else 245 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 247 #endif 248 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 249 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 250 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 251 #ifdef CONFIG_PHYS_64BIT 252 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 253 #else 254 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 255 #endif 256 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 257 258 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 259 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 262 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 263 #else 264 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 265 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 266 #endif 267 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 268 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 269 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 272 #else 273 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 274 #endif 275 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 276 277 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 278 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 281 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 282 #else 283 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 284 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 285 #endif 286 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 287 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 288 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 291 #else 292 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 293 #endif 294 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 295 296 /* controller 4, Base address 203000 */ 297 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 298 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 299 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 300 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 301 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 302 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 303 304 /* Qman/Bman */ 305 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 306 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 309 #else 310 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 311 #endif 312 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 313 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 314 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 315 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 316 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 317 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 318 CONFIG_SYS_BMAN_CENA_SIZE) 319 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 320 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 321 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 322 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 325 #else 326 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 327 #endif 328 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 329 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 330 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 331 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 332 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 333 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 334 CONFIG_SYS_QMAN_CENA_SIZE) 335 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 336 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 337 338 #define CONFIG_SYS_DPAA_FMAN 339 /* Default address of microcode for the Linux Fman driver */ 340 /* 341 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 342 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 343 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 344 */ 345 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 346 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 347 348 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 349 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 350 351 #ifdef CONFIG_SYS_DPAA_FMAN 352 #define CONFIG_FMAN_ENET 353 #endif 354 355 #ifdef CONFIG_PCI 356 #define CONFIG_PCI_INDIRECT_BRIDGE 357 358 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 359 #endif /* CONFIG_PCI */ 360 361 /* SATA */ 362 #ifdef CONFIG_FSL_SATA_V2 363 #define CONFIG_SYS_SATA_MAX_DEVICE 2 364 #define CONFIG_SATA1 365 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 366 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 367 #define CONFIG_SATA2 368 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 369 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 370 371 #define CONFIG_LBA48 372 #endif 373 374 #ifdef CONFIG_FMAN_ENET 375 #define CONFIG_SYS_TBIPA_VALUE 8 376 #define CONFIG_ETHPRIME "FM1@DTSEC4" 377 #endif 378 379 /* 380 * Environment 381 */ 382 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 383 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 384 385 /* 386 * USB 387 */ 388 #define CONFIG_HAS_FSL_DR_USB 389 #define CONFIG_HAS_FSL_MPH_USB 390 391 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 392 #define CONFIG_USB_EHCI_FSL 393 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 394 #define CONFIG_EHCI_IS_TDI 395 /* _VIA_CONTROL_EP */ 396 #endif 397 398 #ifdef CONFIG_MMC 399 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 400 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 401 #endif 402 403 /* 404 * Miscellaneous configurable options 405 */ 406 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 407 408 /* 409 * For booting Linux, the board info and command line data 410 * have to be in the first 64 MB of memory, since this is 411 * the maximum mapped by the Linux kernel during initialization. 412 */ 413 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 414 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 415 416 #ifdef CONFIG_CMD_KGDB 417 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 418 #endif 419 420 /* 421 * Environment Configuration 422 */ 423 #define CONFIG_ROOTPATH "/opt/nfsroot" 424 #define CONFIG_BOOTFILE "uImage" 425 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 426 427 /* default location for tftp and bootm */ 428 #define CONFIG_LOADADDR 1000000 429 430 #define __USB_PHY_TYPE utmi 431 432 #define CONFIG_EXTRA_ENV_SETTINGS \ 433 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 434 "bank_intlv=cs0_cs1;" \ 435 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 436 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 437 "netdev=eth0\0" \ 438 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 439 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 440 "consoledev=ttyS0\0" \ 441 "ramdiskaddr=2000000\0" \ 442 "fdtaddr=1e00000\0" \ 443 "bdev=sda3\0" 444 445 #define CONFIG_HDBOOT \ 446 "setenv bootargs root=/dev/$bdev rw " \ 447 "console=$consoledev,$baudrate $othbootargs;" \ 448 "tftp $loadaddr $bootfile;" \ 449 "tftp $fdtaddr $fdtfile;" \ 450 "bootm $loadaddr - $fdtaddr" 451 452 #define CONFIG_NFSBOOTCOMMAND \ 453 "setenv bootargs root=/dev/nfs rw " \ 454 "nfsroot=$serverip:$rootpath " \ 455 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 456 "console=$consoledev,$baudrate $othbootargs;" \ 457 "tftp $loadaddr $bootfile;" \ 458 "tftp $fdtaddr $fdtfile;" \ 459 "bootm $loadaddr - $fdtaddr" 460 461 #define CONFIG_RAMBOOTCOMMAND \ 462 "setenv bootargs root=/dev/ram rw " \ 463 "console=$consoledev,$baudrate $othbootargs;" \ 464 "tftp $ramdiskaddr $ramdiskfile;" \ 465 "tftp $loadaddr $bootfile;" \ 466 "tftp $fdtaddr $fdtfile;" \ 467 "bootm $loadaddr $ramdiskaddr $fdtaddr" 468 469 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 470 471 #include <asm/fsl_secure_boot.h> 472 473 #endif /* __CONFIG_H */ 474