1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_SDCARD 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE3 19 #define CONFIG_PCIE4 20 #ifdef CONFIG_ARCH_P5020 21 #define CONFIG_SYS_FSL_RAID_ENGINE 22 #define CONFIG_SYS_DPAA_RMAN 23 #endif 24 #define CONFIG_SYS_DPAA_PME 25 26 /* 27 * Corenet DS style board configuration file 28 */ 29 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 32 #if defined(CONFIG_ARCH_P5020) 33 #define CONFIG_SYS_CLK_FREQ 133000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 35 #elif defined(CONFIG_ARCH_P5040) 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MP /* support multiple processors */ 43 44 #define CONFIG_SYS_MMC_MAX_DEVICE 1 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 48 #endif 49 50 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 51 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 52 #define CONFIG_PCIE1 /* PCIE controller 1 */ 53 #define CONFIG_PCIE2 /* PCIE controller 2 */ 54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 56 57 #define CONFIG_ENV_OVERWRITE 58 59 #define CONFIG_SYS_NO_FLASH 60 61 #if defined(CONFIG_SDCARD) 62 #define CONFIG_SYS_EXTRA_ENV_RELOC 63 #define CONFIG_ENV_IS_IN_MMC 64 #define CONFIG_FSL_FIXED_MMC_LOCATION 65 #define CONFIG_SYS_MMC_ENV_DEV 0 66 #define CONFIG_ENV_SIZE 0x2000 67 #define CONFIG_ENV_OFFSET (512 * 1658) 68 #endif 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_SYS_CACHE_STASHING 74 #define CONFIG_BACKSIDE_L2_CACHE 75 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 76 #define CONFIG_BTB /* toggle branch predition */ 77 #define CONFIG_DDR_ECC 78 #ifdef CONFIG_DDR_ECC 79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 80 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 81 #endif 82 83 #define CONFIG_ENABLE_36BIT_PHYS 84 85 #ifdef CONFIG_PHYS_64BIT 86 #define CONFIG_ADDR_MAP 87 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 88 #endif 89 90 /* test POST memory test */ 91 #undef CONFIG_POST 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 #define CONFIG_SYS_ALT_MEMTEST 95 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 96 97 /* 98 * Config the L3 Cache as L3 SRAM 99 */ 100 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 101 #ifdef CONFIG_PHYS_64BIT 102 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 103 #else 104 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 105 #endif 106 #define CONFIG_SYS_L3_SIZE (1024 << 10) 107 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 108 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_SYS_DCSRBAR 0xf0000000 111 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 112 #endif 113 114 /* 115 * DDR Setup 116 */ 117 #define CONFIG_VERY_BIG_RAM 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 123 124 #define CONFIG_DDR_SPD 125 126 #define CONFIG_SYS_SPD_BUS_NUM 1 127 #define SPD_EEPROM_ADDRESS1 0x51 128 #define SPD_EEPROM_ADDRESS2 0x52 129 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 130 131 /* 132 * Local Bus Definitions 133 */ 134 135 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 138 #else 139 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 140 #endif 141 142 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 143 #ifdef CONFIG_PHYS_64BIT 144 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 145 #else 146 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 147 #endif 148 149 /* Set the local bus clock 1/16 of platform clock */ 150 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 151 152 #define CONFIG_SYS_BR0_PRELIM \ 153 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 154 #define CONFIG_SYS_BR1_PRELIM \ 155 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 156 157 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 158 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 159 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 161 162 #if defined(CONFIG_RAMBOOT_PBL) 163 #define CONFIG_SYS_RAMBOOT 164 #endif 165 166 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 167 #define CONFIG_MISC_INIT_R 168 169 #define CONFIG_HWCONFIG 170 171 /* define to use L1 as initial stack */ 172 #define CONFIG_L1_INIT_RAM 173 #define CONFIG_SYS_INIT_RAM_LOCK 174 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 178 /* The assembler doesn't like typecast */ 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 180 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 181 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 182 #else 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 186 #endif 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 193 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 194 195 /* Serial Port - controlled on board with jumper J8 196 * open - index 2 197 * shorted - index 1 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE 1 202 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 203 204 #define CONFIG_SYS_BAUDRATE_TABLE \ 205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 206 207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 209 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 210 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 211 212 /* I2C */ 213 #define CONFIG_SYS_I2C 214 #define CONFIG_SYS_I2C_FSL 215 #define CONFIG_I2C_MULTI_BUS 216 #define CONFIG_I2C_CMD_TREE 217 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 218 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 219 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 220 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 221 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 223 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 224 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 226 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 227 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 229 230 #define CONFIG_ID_EEPROM 231 #define CONFIG_SYS_I2C_EEPROM_NXID 232 #define CONFIG_SYS_EEPROM_BUS_NUM 0 233 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 235 236 #define CONFIG_SYS_I2C_GENERIC_MAC 237 #define CONFIG_SYS_I2C_MAC1_BUS 3 238 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 239 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 240 #define CONFIG_SYS_I2C_MAC2_BUS 0 241 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 242 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 243 244 #define CONFIG_CMD_DATE 1 245 #define CONFIG_RTC_MCP79411 1 246 #define CONFIG_SYS_RTC_BUS_NUM 3 247 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 248 249 /* 250 * eSPI - Enhanced SPI 251 */ 252 253 /* 254 * General PCI 255 * Memory space is mapped 1-1, but I/O space must start from 0. 256 */ 257 258 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 259 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 262 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 263 #else 264 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 265 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 266 #endif 267 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 268 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 269 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 272 #else 273 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 274 #endif 275 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 276 277 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 278 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 281 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 282 #else 283 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 284 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 285 #endif 286 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 287 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 288 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 291 #else 292 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 293 #endif 294 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 295 296 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 297 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 300 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 301 #else 302 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 303 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 304 #endif 305 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 306 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 307 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 310 #else 311 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 312 #endif 313 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 314 315 /* controller 4, Base address 203000 */ 316 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 317 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 318 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 319 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 320 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 321 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 322 323 /* Qman/Bman */ 324 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 325 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 326 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 327 #ifdef CONFIG_PHYS_64BIT 328 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 329 #else 330 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 331 #endif 332 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 333 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 334 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 335 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 336 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 337 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 338 CONFIG_SYS_BMAN_CENA_SIZE) 339 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 340 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 341 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 342 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 345 #else 346 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 347 #endif 348 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 349 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 350 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 351 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 352 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 353 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 354 CONFIG_SYS_QMAN_CENA_SIZE) 355 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 356 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 357 358 #define CONFIG_SYS_DPAA_FMAN 359 /* Default address of microcode for the Linux Fman driver */ 360 /* 361 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 362 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 363 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 364 */ 365 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 366 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 367 368 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 369 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 370 371 #ifdef CONFIG_SYS_DPAA_FMAN 372 #define CONFIG_FMAN_ENET 373 #define CONFIG_PHY_MICREL 374 #define CONFIG_PHY_MICREL_KSZ9021 375 #endif 376 377 #ifdef CONFIG_PCI 378 #define CONFIG_PCI_INDIRECT_BRIDGE 379 #define CONFIG_NET_MULTI 380 381 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 382 #endif /* CONFIG_PCI */ 383 384 /* SATA */ 385 #ifdef CONFIG_FSL_SATA_V2 386 #define CONFIG_LIBATA 387 #define CONFIG_FSL_SATA 388 389 #define CONFIG_SYS_SATA_MAX_DEVICE 2 390 #define CONFIG_SATA1 391 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 392 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 393 #define CONFIG_SATA2 394 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 395 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 396 397 #define CONFIG_LBA48 398 #define CONFIG_CMD_SATA 399 #endif 400 401 #ifdef CONFIG_FMAN_ENET 402 #define CONFIG_SYS_TBIPA_VALUE 8 403 #define CONFIG_MII /* MII PHY management */ 404 #define CONFIG_ETHPRIME "FM1@DTSEC4" 405 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 406 #endif 407 408 /* 409 * Environment 410 */ 411 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 413 414 /* 415 * Command line configuration. 416 */ 417 #define CONFIG_CMD_ERRATA 418 #define CONFIG_CMD_IRQ 419 #define CONFIG_CMD_REGINFO 420 421 #ifdef CONFIG_PCI 422 #define CONFIG_CMD_PCI 423 #endif 424 425 /* 426 * USB 427 */ 428 #define CONFIG_HAS_FSL_DR_USB 429 #define CONFIG_HAS_FSL_MPH_USB 430 431 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 432 #define CONFIG_USB_EHCI 433 #define CONFIG_USB_EHCI_FSL 434 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 435 #define CONFIG_EHCI_IS_TDI 436 #define CONFIG_SYS_USB_EVENT_POLL 437 /* _VIA_CONTROL_EP */ 438 #endif 439 440 #ifdef CONFIG_MMC 441 #define CONFIG_FSL_ESDHC 442 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 443 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 444 #endif 445 446 /* 447 * Miscellaneous configurable options 448 */ 449 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 450 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 451 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 452 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 453 #ifdef CONFIG_CMD_KGDB 454 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 455 #else 456 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 457 #endif 458 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 459 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 460 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 461 462 /* 463 * For booting Linux, the board info and command line data 464 * have to be in the first 64 MB of memory, since this is 465 * the maximum mapped by the Linux kernel during initialization. 466 */ 467 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 468 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 469 470 #ifdef CONFIG_CMD_KGDB 471 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 472 #endif 473 474 /* 475 * Environment Configuration 476 */ 477 #define CONFIG_ROOTPATH "/opt/nfsroot" 478 #define CONFIG_BOOTFILE "uImage" 479 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 480 481 /* default location for tftp and bootm */ 482 #define CONFIG_LOADADDR 1000000 483 484 485 #define CONFIG_BAUDRATE 115200 486 487 #define __USB_PHY_TYPE utmi 488 489 #define CONFIG_EXTRA_ENV_SETTINGS \ 490 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 491 "bank_intlv=cs0_cs1;" \ 492 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 493 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 494 "netdev=eth0\0" \ 495 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 496 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 497 "consoledev=ttyS0\0" \ 498 "ramdiskaddr=2000000\0" \ 499 "fdtaddr=1e00000\0" \ 500 "bdev=sda3\0" 501 502 #define CONFIG_HDBOOT \ 503 "setenv bootargs root=/dev/$bdev rw " \ 504 "console=$consoledev,$baudrate $othbootargs;" \ 505 "tftp $loadaddr $bootfile;" \ 506 "tftp $fdtaddr $fdtfile;" \ 507 "bootm $loadaddr - $fdtaddr" 508 509 #define CONFIG_NFSBOOTCOMMAND \ 510 "setenv bootargs root=/dev/nfs rw " \ 511 "nfsroot=$serverip:$rootpath " \ 512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 513 "console=$consoledev,$baudrate $othbootargs;" \ 514 "tftp $loadaddr $bootfile;" \ 515 "tftp $fdtaddr $fdtfile;" \ 516 "bootm $loadaddr - $fdtaddr" 517 518 #define CONFIG_RAMBOOTCOMMAND \ 519 "setenv bootargs root=/dev/ram rw " \ 520 "console=$consoledev,$baudrate $othbootargs;" \ 521 "tftp $ramdiskaddr $ramdiskfile;" \ 522 "tftp $loadaddr $bootfile;" \ 523 "tftp $fdtaddr $fdtfile;" \ 524 "bootm $loadaddr $ramdiskaddr $fdtaddr" 525 526 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 527 528 #include <asm/fsl_secure_boot.h> 529 530 #ifdef CONFIG_SECURE_BOOT 531 #endif 532 533 #endif /* __CONFIG_H */ 534