1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_SDCARD 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE3 19 #define CONFIG_PCIE4 20 #ifdef CONFIG_ARCH_P5020 21 #define CONFIG_SYS_FSL_RAID_ENGINE 22 #define CONFIG_SYS_DPAA_RMAN 23 #endif 24 #define CONFIG_SYS_DPAA_PME 25 26 /* 27 * Corenet DS style board configuration file 28 */ 29 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 32 #if defined(CONFIG_ARCH_P5020) 33 #define CONFIG_SYS_CLK_FREQ 133000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 35 #elif defined(CONFIG_ARCH_P5040) 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MP /* support multiple processors */ 43 44 #define CONFIG_SYS_MMC_MAX_DEVICE 1 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 48 #endif 49 50 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 51 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 52 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 53 #define CONFIG_PCIE1 /* PCIE controller 1 */ 54 #define CONFIG_PCIE2 /* PCIE controller 2 */ 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_SYS_NO_FLASH 61 62 #if defined(CONFIG_SDCARD) 63 #define CONFIG_SYS_EXTRA_ENV_RELOC 64 #define CONFIG_ENV_IS_IN_MMC 65 #define CONFIG_FSL_FIXED_MMC_LOCATION 66 #define CONFIG_SYS_MMC_ENV_DEV 0 67 #define CONFIG_ENV_SIZE 0x2000 68 #define CONFIG_ENV_OFFSET (512 * 1658) 69 #endif 70 71 /* 72 * These can be toggled for performance analysis, otherwise use default. 73 */ 74 #define CONFIG_SYS_CACHE_STASHING 75 #define CONFIG_BACKSIDE_L2_CACHE 76 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 77 #define CONFIG_BTB /* toggle branch predition */ 78 #define CONFIG_DDR_ECC 79 #ifdef CONFIG_DDR_ECC 80 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 81 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 82 #endif 83 84 #define CONFIG_ENABLE_36BIT_PHYS 85 86 #ifdef CONFIG_PHYS_64BIT 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 #endif 90 91 /* test POST memory test */ 92 #undef CONFIG_POST 93 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 94 #define CONFIG_SYS_MEMTEST_END 0x00400000 95 #define CONFIG_SYS_ALT_MEMTEST 96 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 97 98 /* 99 * Config the L3 Cache as L3 SRAM 100 */ 101 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 104 #else 105 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 106 #endif 107 #define CONFIG_SYS_L3_SIZE (1024 << 10) 108 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 109 110 #ifdef CONFIG_PHYS_64BIT 111 #define CONFIG_SYS_DCSRBAR 0xf0000000 112 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 113 #endif 114 115 /* 116 * DDR Setup 117 */ 118 #define CONFIG_VERY_BIG_RAM 119 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 121 122 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 123 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 124 125 #define CONFIG_DDR_SPD 126 127 #define CONFIG_SYS_SPD_BUS_NUM 1 128 #define SPD_EEPROM_ADDRESS1 0x51 129 #define SPD_EEPROM_ADDRESS2 0x52 130 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 131 132 /* 133 * Local Bus Definitions 134 */ 135 136 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 139 #else 140 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 141 #endif 142 143 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 146 #else 147 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 148 #endif 149 150 /* Set the local bus clock 1/16 of platform clock */ 151 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 152 153 #define CONFIG_SYS_BR0_PRELIM \ 154 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 155 #define CONFIG_SYS_BR1_PRELIM \ 156 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 157 158 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 159 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 160 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 162 163 #if defined(CONFIG_RAMBOOT_PBL) 164 #define CONFIG_SYS_RAMBOOT 165 #endif 166 167 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 168 #define CONFIG_MISC_INIT_R 169 170 #define CONFIG_HWCONFIG 171 172 /* define to use L1 as initial stack */ 173 #define CONFIG_L1_INIT_RAM 174 #define CONFIG_SYS_INIT_RAM_LOCK 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 176 #ifdef CONFIG_PHYS_64BIT 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 179 /* The assembler doesn't like typecast */ 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 181 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 182 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 183 #else 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 187 #endif 188 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 189 190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 194 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 195 196 /* Serial Port - controlled on board with jumper J8 197 * open - index 2 198 * shorted - index 1 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #define CONFIG_SYS_NS16550_SERIAL 202 #define CONFIG_SYS_NS16550_REG_SIZE 1 203 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 204 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 207 208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 210 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 211 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 212 213 /* I2C */ 214 #define CONFIG_SYS_I2C 215 #define CONFIG_SYS_I2C_FSL 216 #define CONFIG_I2C_MULTI_BUS 217 #define CONFIG_I2C_CMD_TREE 218 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 219 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 221 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 222 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 224 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 225 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 227 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 228 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 229 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 230 231 #define CONFIG_ID_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_NXID 233 #define CONFIG_SYS_EEPROM_BUS_NUM 0 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 235 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 236 237 #define CONFIG_SYS_I2C_GENERIC_MAC 238 #define CONFIG_SYS_I2C_MAC1_BUS 3 239 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 240 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 241 #define CONFIG_SYS_I2C_MAC2_BUS 0 242 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 243 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 244 245 #define CONFIG_CMD_DATE 1 246 #define CONFIG_RTC_MCP79411 1 247 #define CONFIG_SYS_RTC_BUS_NUM 3 248 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 249 250 /* 251 * eSPI - Enhanced SPI 252 */ 253 254 /* 255 * General PCI 256 * Memory space is mapped 1-1, but I/O space must start from 0. 257 */ 258 259 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 260 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 263 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 264 #else 265 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 266 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 267 #endif 268 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 269 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 270 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 273 #else 274 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 275 #endif 276 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 277 278 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 279 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 282 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 283 #else 284 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 285 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 286 #endif 287 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 288 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 289 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 290 #ifdef CONFIG_PHYS_64BIT 291 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 292 #else 293 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 294 #endif 295 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 296 297 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 298 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 301 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 302 #else 303 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 304 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 305 #endif 306 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 307 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 308 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 311 #else 312 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 313 #endif 314 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 315 316 /* controller 4, Base address 203000 */ 317 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 318 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 319 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 320 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 321 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 322 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 323 324 /* Qman/Bman */ 325 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 326 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 327 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 330 #else 331 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 332 #endif 333 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 334 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 335 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 336 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 337 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 338 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 339 CONFIG_SYS_BMAN_CENA_SIZE) 340 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 341 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 342 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 343 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 346 #else 347 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 348 #endif 349 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 350 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 351 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 352 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 353 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 354 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 355 CONFIG_SYS_QMAN_CENA_SIZE) 356 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 357 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 358 359 #define CONFIG_SYS_DPAA_FMAN 360 /* Default address of microcode for the Linux Fman driver */ 361 /* 362 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 363 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 364 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 365 */ 366 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 367 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 368 369 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 370 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 371 372 #ifdef CONFIG_SYS_DPAA_FMAN 373 #define CONFIG_FMAN_ENET 374 #define CONFIG_PHY_MICREL 375 #define CONFIG_PHY_MICREL_KSZ9021 376 #endif 377 378 #ifdef CONFIG_PCI 379 #define CONFIG_PCI_INDIRECT_BRIDGE 380 #define CONFIG_NET_MULTI 381 382 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 383 #endif /* CONFIG_PCI */ 384 385 /* SATA */ 386 #ifdef CONFIG_FSL_SATA_V2 387 #define CONFIG_LIBATA 388 #define CONFIG_FSL_SATA 389 390 #define CONFIG_SYS_SATA_MAX_DEVICE 2 391 #define CONFIG_SATA1 392 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 393 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 394 #define CONFIG_SATA2 395 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 396 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 397 398 #define CONFIG_LBA48 399 #define CONFIG_CMD_SATA 400 #endif 401 402 #ifdef CONFIG_FMAN_ENET 403 #define CONFIG_SYS_TBIPA_VALUE 8 404 #define CONFIG_MII /* MII PHY management */ 405 #define CONFIG_ETHPRIME "FM1@DTSEC4" 406 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 407 #endif 408 409 /* 410 * Environment 411 */ 412 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 413 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 414 415 /* 416 * Command line configuration. 417 */ 418 #define CONFIG_CMD_ERRATA 419 #define CONFIG_CMD_IRQ 420 #define CONFIG_CMD_REGINFO 421 422 #ifdef CONFIG_PCI 423 #define CONFIG_CMD_PCI 424 #endif 425 426 /* 427 * USB 428 */ 429 #define CONFIG_HAS_FSL_DR_USB 430 #define CONFIG_HAS_FSL_MPH_USB 431 432 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 433 #define CONFIG_USB_EHCI 434 #define CONFIG_USB_EHCI_FSL 435 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 436 #define CONFIG_EHCI_IS_TDI 437 #define CONFIG_SYS_USB_EVENT_POLL 438 /* _VIA_CONTROL_EP */ 439 #endif 440 441 #ifdef CONFIG_MMC 442 #define CONFIG_FSL_ESDHC 443 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 444 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 445 #define CONFIG_GENERIC_MMC 446 #endif 447 448 /* 449 * Miscellaneous configurable options 450 */ 451 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 452 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 453 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 454 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 455 #ifdef CONFIG_CMD_KGDB 456 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 457 #else 458 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 459 #endif 460 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 461 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 463 464 /* 465 * For booting Linux, the board info and command line data 466 * have to be in the first 64 MB of memory, since this is 467 * the maximum mapped by the Linux kernel during initialization. 468 */ 469 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 470 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 471 472 #ifdef CONFIG_CMD_KGDB 473 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 474 #endif 475 476 /* 477 * Environment Configuration 478 */ 479 #define CONFIG_ROOTPATH "/opt/nfsroot" 480 #define CONFIG_BOOTFILE "uImage" 481 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 482 483 /* default location for tftp and bootm */ 484 #define CONFIG_LOADADDR 1000000 485 486 487 #define CONFIG_BAUDRATE 115200 488 489 #define __USB_PHY_TYPE utmi 490 491 #define CONFIG_EXTRA_ENV_SETTINGS \ 492 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 493 "bank_intlv=cs0_cs1;" \ 494 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 495 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 496 "netdev=eth0\0" \ 497 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 498 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 499 "consoledev=ttyS0\0" \ 500 "ramdiskaddr=2000000\0" \ 501 "fdtaddr=1e00000\0" \ 502 "bdev=sda3\0" 503 504 #define CONFIG_HDBOOT \ 505 "setenv bootargs root=/dev/$bdev rw " \ 506 "console=$consoledev,$baudrate $othbootargs;" \ 507 "tftp $loadaddr $bootfile;" \ 508 "tftp $fdtaddr $fdtfile;" \ 509 "bootm $loadaddr - $fdtaddr" 510 511 #define CONFIG_NFSBOOTCOMMAND \ 512 "setenv bootargs root=/dev/nfs rw " \ 513 "nfsroot=$serverip:$rootpath " \ 514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $loadaddr $bootfile;" \ 517 "tftp $fdtaddr $fdtfile;" \ 518 "bootm $loadaddr - $fdtaddr" 519 520 #define CONFIG_RAMBOOTCOMMAND \ 521 "setenv bootargs root=/dev/ram rw " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "tftp $ramdiskaddr $ramdiskfile;" \ 524 "tftp $loadaddr $bootfile;" \ 525 "tftp $fdtaddr $fdtfile;" \ 526 "bootm $loadaddr $ramdiskaddr $fdtaddr" 527 528 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 529 530 #include <asm/fsl_secure_boot.h> 531 532 #ifdef CONFIG_SECURE_BOOT 533 #endif 534 535 #endif /* __CONFIG_H */ 536