1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 11 #error Must call Cyrus CONFIG with a specific CPU enabled. 12 #endif 13 14 #define CONFIG_SDCARD 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE3 17 #define CONFIG_PCIE4 18 #ifdef CONFIG_ARCH_P5020 19 #define CONFIG_SYS_FSL_RAID_ENGINE 20 #define CONFIG_SYS_DPAA_RMAN 21 #endif 22 #define CONFIG_SYS_DPAA_PME 23 24 /* 25 * Corenet DS style board configuration file 26 */ 27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 29 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 30 #if defined(CONFIG_ARCH_P5020) 31 #define CONFIG_SYS_CLK_FREQ 133000000 32 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 33 #elif defined(CONFIG_ARCH_P5040) 34 #define CONFIG_SYS_CLK_FREQ 100000000 35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 40 #define CONFIG_MP /* support multiple processors */ 41 42 #define CONFIG_SYS_MMC_MAX_DEVICE 1 43 44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 45 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 46 #define CONFIG_PCIE1 /* PCIE controller 1 */ 47 #define CONFIG_PCIE2 /* PCIE controller 2 */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50 51 #define CONFIG_ENV_OVERWRITE 52 53 #if defined(CONFIG_SDCARD) 54 #define CONFIG_SYS_EXTRA_ENV_RELOC 55 #define CONFIG_FSL_FIXED_MMC_LOCATION 56 #define CONFIG_SYS_MMC_ENV_DEV 0 57 #define CONFIG_ENV_SIZE 0x2000 58 #define CONFIG_ENV_OFFSET (512 * 1658) 59 #endif 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_SYS_CACHE_STASHING 65 #define CONFIG_BACKSIDE_L2_CACHE 66 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 67 #define CONFIG_BTB /* toggle branch predition */ 68 #define CONFIG_DDR_ECC 69 #ifdef CONFIG_DDR_ECC 70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 71 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 72 #endif 73 74 #define CONFIG_ENABLE_36BIT_PHYS 75 76 #ifdef CONFIG_PHYS_64BIT 77 #define CONFIG_ADDR_MAP 78 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 79 #endif 80 81 /* test POST memory test */ 82 #undef CONFIG_POST 83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_END 0x00400000 85 #define CONFIG_SYS_ALT_MEMTEST 86 87 /* 88 * Config the L3 Cache as L3 SRAM 89 */ 90 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 91 #ifdef CONFIG_PHYS_64BIT 92 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 93 #else 94 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 95 #endif 96 #define CONFIG_SYS_L3_SIZE (1024 << 10) 97 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 98 99 #ifdef CONFIG_PHYS_64BIT 100 #define CONFIG_SYS_DCSRBAR 0xf0000000 101 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 102 #endif 103 104 /* 105 * DDR Setup 106 */ 107 #define CONFIG_VERY_BIG_RAM 108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 110 111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 112 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 113 114 #define CONFIG_DDR_SPD 115 116 #define CONFIG_SYS_SPD_BUS_NUM 1 117 #define SPD_EEPROM_ADDRESS1 0x51 118 #define SPD_EEPROM_ADDRESS2 0x52 119 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 120 121 /* 122 * Local Bus Definitions 123 */ 124 125 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 128 #else 129 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 130 #endif 131 132 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 135 #else 136 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 137 #endif 138 139 /* Set the local bus clock 1/16 of platform clock */ 140 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 141 142 #define CONFIG_SYS_BR0_PRELIM \ 143 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 144 #define CONFIG_SYS_BR1_PRELIM \ 145 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 146 147 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 148 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 149 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 151 152 #if defined(CONFIG_RAMBOOT_PBL) 153 #define CONFIG_SYS_RAMBOOT 154 #endif 155 156 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 157 #define CONFIG_MISC_INIT_R 158 159 #define CONFIG_HWCONFIG 160 161 /* define to use L1 as initial stack */ 162 #define CONFIG_L1_INIT_RAM 163 #define CONFIG_SYS_INIT_RAM_LOCK 164 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 168 /* The assembler doesn't like typecast */ 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 170 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 171 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 172 #else 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 176 #endif 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 178 179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 181 182 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 183 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 184 185 /* Serial Port - controlled on board with jumper J8 186 * open - index 2 187 * shorted - index 1 188 */ 189 #define CONFIG_CONS_INDEX 1 190 #define CONFIG_SYS_NS16550_SERIAL 191 #define CONFIG_SYS_NS16550_REG_SIZE 1 192 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 193 194 #define CONFIG_SYS_BAUDRATE_TABLE \ 195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 196 197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 199 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 200 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 201 202 /* I2C */ 203 #define CONFIG_SYS_I2C 204 #define CONFIG_SYS_I2C_FSL 205 #define CONFIG_I2C_MULTI_BUS 206 #define CONFIG_I2C_CMD_TREE 207 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 210 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 211 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 213 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 214 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 216 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 217 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 219 220 #define CONFIG_ID_EEPROM 221 #define CONFIG_SYS_I2C_EEPROM_NXID 222 #define CONFIG_SYS_EEPROM_BUS_NUM 0 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 225 226 #define CONFIG_SYS_I2C_GENERIC_MAC 227 #define CONFIG_SYS_I2C_MAC1_BUS 3 228 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 229 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 230 #define CONFIG_SYS_I2C_MAC2_BUS 0 231 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 232 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 233 234 #define CONFIG_RTC_MCP79411 1 235 #define CONFIG_SYS_RTC_BUS_NUM 3 236 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 237 238 /* 239 * eSPI - Enhanced SPI 240 */ 241 242 /* 243 * General PCI 244 * Memory space is mapped 1-1, but I/O space must start from 0. 245 */ 246 247 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 248 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 251 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 252 #else 253 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 254 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 255 #endif 256 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 257 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 258 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 259 #ifdef CONFIG_PHYS_64BIT 260 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 261 #else 262 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 263 #endif 264 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 265 266 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 267 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 270 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 271 #else 272 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 273 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 274 #endif 275 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 276 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 277 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 280 #else 281 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 282 #endif 283 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 284 285 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 286 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 289 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 290 #else 291 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 292 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 293 #endif 294 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 295 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 296 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 299 #else 300 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 301 #endif 302 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 303 304 /* controller 4, Base address 203000 */ 305 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 306 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 307 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 308 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 309 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 310 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 311 312 /* Qman/Bman */ 313 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 314 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 315 #ifdef CONFIG_PHYS_64BIT 316 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 317 #else 318 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 319 #endif 320 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 321 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 322 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 323 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 324 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 326 CONFIG_SYS_BMAN_CENA_SIZE) 327 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 328 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 329 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 330 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 333 #else 334 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 335 #endif 336 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 337 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 338 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 339 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 340 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 341 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 342 CONFIG_SYS_QMAN_CENA_SIZE) 343 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 344 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 345 346 #define CONFIG_SYS_DPAA_FMAN 347 /* Default address of microcode for the Linux Fman driver */ 348 /* 349 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 350 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 351 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 352 */ 353 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 354 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 355 356 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 357 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 358 359 #ifdef CONFIG_SYS_DPAA_FMAN 360 #define CONFIG_FMAN_ENET 361 #endif 362 363 #ifdef CONFIG_PCI 364 #define CONFIG_PCI_INDIRECT_BRIDGE 365 366 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 367 #endif /* CONFIG_PCI */ 368 369 /* SATA */ 370 #ifdef CONFIG_FSL_SATA_V2 371 #define CONFIG_SYS_SATA_MAX_DEVICE 2 372 #define CONFIG_SATA1 373 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 374 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 375 #define CONFIG_SATA2 376 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 377 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 378 379 #define CONFIG_LBA48 380 #endif 381 382 #ifdef CONFIG_FMAN_ENET 383 #define CONFIG_SYS_TBIPA_VALUE 8 384 #define CONFIG_MII /* MII PHY management */ 385 #define CONFIG_ETHPRIME "FM1@DTSEC4" 386 #endif 387 388 /* 389 * Environment 390 */ 391 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 392 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 393 394 /* 395 * USB 396 */ 397 #define CONFIG_HAS_FSL_DR_USB 398 #define CONFIG_HAS_FSL_MPH_USB 399 400 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 401 #define CONFIG_USB_EHCI_FSL 402 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 403 #define CONFIG_EHCI_IS_TDI 404 /* _VIA_CONTROL_EP */ 405 #endif 406 407 #ifdef CONFIG_MMC 408 #define CONFIG_FSL_ESDHC 409 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 410 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 411 #endif 412 413 /* 414 * Miscellaneous configurable options 415 */ 416 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 417 418 /* 419 * For booting Linux, the board info and command line data 420 * have to be in the first 64 MB of memory, since this is 421 * the maximum mapped by the Linux kernel during initialization. 422 */ 423 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 424 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 425 426 #ifdef CONFIG_CMD_KGDB 427 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 428 #endif 429 430 /* 431 * Environment Configuration 432 */ 433 #define CONFIG_ROOTPATH "/opt/nfsroot" 434 #define CONFIG_BOOTFILE "uImage" 435 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 436 437 /* default location for tftp and bootm */ 438 #define CONFIG_LOADADDR 1000000 439 440 #define __USB_PHY_TYPE utmi 441 442 #define CONFIG_EXTRA_ENV_SETTINGS \ 443 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 444 "bank_intlv=cs0_cs1;" \ 445 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 446 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 447 "netdev=eth0\0" \ 448 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 449 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 450 "consoledev=ttyS0\0" \ 451 "ramdiskaddr=2000000\0" \ 452 "fdtaddr=1e00000\0" \ 453 "bdev=sda3\0" 454 455 #define CONFIG_HDBOOT \ 456 "setenv bootargs root=/dev/$bdev rw " \ 457 "console=$consoledev,$baudrate $othbootargs;" \ 458 "tftp $loadaddr $bootfile;" \ 459 "tftp $fdtaddr $fdtfile;" \ 460 "bootm $loadaddr - $fdtaddr" 461 462 #define CONFIG_NFSBOOTCOMMAND \ 463 "setenv bootargs root=/dev/nfs rw " \ 464 "nfsroot=$serverip:$rootpath " \ 465 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 466 "console=$consoledev,$baudrate $othbootargs;" \ 467 "tftp $loadaddr $bootfile;" \ 468 "tftp $fdtaddr $fdtfile;" \ 469 "bootm $loadaddr - $fdtaddr" 470 471 #define CONFIG_RAMBOOTCOMMAND \ 472 "setenv bootargs root=/dev/ram rw " \ 473 "console=$consoledev,$baudrate $othbootargs;" \ 474 "tftp $ramdiskaddr $ramdiskfile;" \ 475 "tftp $loadaddr $bootfile;" \ 476 "tftp $fdtaddr $fdtfile;" \ 477 "bootm $loadaddr $ramdiskaddr $fdtaddr" 478 479 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 480 481 #include <asm/fsl_secure_boot.h> 482 483 #ifdef CONFIG_SECURE_BOOT 484 #endif 485 486 #endif /* __CONFIG_H */ 487