1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 11 #error Must call Cyrus CONFIG with a specific CPU enabled. 12 #endif 13 14 #define CONFIG_SDCARD 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE3 17 #define CONFIG_PCIE4 18 #ifdef CONFIG_ARCH_P5020 19 #define CONFIG_SYS_FSL_RAID_ENGINE 20 #define CONFIG_SYS_DPAA_RMAN 21 #endif 22 #define CONFIG_SYS_DPAA_PME 23 24 /* 25 * Corenet DS style board configuration file 26 */ 27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 29 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 30 #if defined(CONFIG_ARCH_P5020) 31 #define CONFIG_SYS_CLK_FREQ 133000000 32 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 33 #elif defined(CONFIG_ARCH_P5040) 34 #define CONFIG_SYS_CLK_FREQ 100000000 35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 40 #define CONFIG_MP /* support multiple processors */ 41 42 #define CONFIG_SYS_MMC_MAX_DEVICE 1 43 44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 45 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 46 #define CONFIG_PCIE1 /* PCIE controller 1 */ 47 #define CONFIG_PCIE2 /* PCIE controller 2 */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50 51 #define CONFIG_ENV_OVERWRITE 52 53 #if defined(CONFIG_SDCARD) 54 #define CONFIG_SYS_EXTRA_ENV_RELOC 55 #define CONFIG_FSL_FIXED_MMC_LOCATION 56 #define CONFIG_SYS_MMC_ENV_DEV 0 57 #define CONFIG_ENV_SIZE 0x2000 58 #define CONFIG_ENV_OFFSET (512 * 1658) 59 #endif 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_SYS_CACHE_STASHING 65 #define CONFIG_BACKSIDE_L2_CACHE 66 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 67 #define CONFIG_BTB /* toggle branch predition */ 68 #define CONFIG_DDR_ECC 69 #ifdef CONFIG_DDR_ECC 70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 71 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 72 #endif 73 74 #define CONFIG_ENABLE_36BIT_PHYS 75 76 #ifdef CONFIG_PHYS_64BIT 77 #define CONFIG_ADDR_MAP 78 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 79 #endif 80 81 /* test POST memory test */ 82 #undef CONFIG_POST 83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_END 0x00400000 85 86 /* 87 * Config the L3 Cache as L3 SRAM 88 */ 89 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 92 #else 93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 94 #endif 95 #define CONFIG_SYS_L3_SIZE (1024 << 10) 96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 97 98 #ifdef CONFIG_PHYS_64BIT 99 #define CONFIG_SYS_DCSRBAR 0xf0000000 100 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 101 #endif 102 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_VERY_BIG_RAM 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 111 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 112 113 #define CONFIG_DDR_SPD 114 115 #define CONFIG_SYS_SPD_BUS_NUM 1 116 #define SPD_EEPROM_ADDRESS1 0x51 117 #define SPD_EEPROM_ADDRESS2 0x52 118 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 119 120 /* 121 * Local Bus Definitions 122 */ 123 124 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 127 #else 128 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 129 #endif 130 131 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 134 #else 135 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 136 #endif 137 138 /* Set the local bus clock 1/16 of platform clock */ 139 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 140 141 #define CONFIG_SYS_BR0_PRELIM \ 142 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 143 #define CONFIG_SYS_BR1_PRELIM \ 144 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 145 146 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 147 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 148 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 150 151 #if defined(CONFIG_RAMBOOT_PBL) 152 #define CONFIG_SYS_RAMBOOT 153 #endif 154 155 #define CONFIG_MISC_INIT_R 156 157 #define CONFIG_HWCONFIG 158 159 /* define to use L1 as initial stack */ 160 #define CONFIG_L1_INIT_RAM 161 #define CONFIG_SYS_INIT_RAM_LOCK 162 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 163 #ifdef CONFIG_PHYS_64BIT 164 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 166 /* The assembler doesn't like typecast */ 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 168 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 169 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 170 #else 171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 174 #endif 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 176 177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 181 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 182 183 /* Serial Port - controlled on board with jumper J8 184 * open - index 2 185 * shorted - index 1 186 */ 187 #define CONFIG_SYS_NS16550_SERIAL 188 #define CONFIG_SYS_NS16550_REG_SIZE 1 189 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 190 191 #define CONFIG_SYS_BAUDRATE_TABLE \ 192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 193 194 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 195 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 196 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 197 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 198 199 /* I2C */ 200 #define CONFIG_SYS_I2C 201 #define CONFIG_SYS_I2C_FSL 202 #define CONFIG_I2C_MULTI_BUS 203 #define CONFIG_I2C_CMD_TREE 204 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 207 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 208 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 209 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 210 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 211 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 213 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 214 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 216 217 #define CONFIG_ID_EEPROM 218 #define CONFIG_SYS_I2C_EEPROM_NXID 219 #define CONFIG_SYS_EEPROM_BUS_NUM 0 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 222 223 #define CONFIG_SYS_I2C_GENERIC_MAC 224 #define CONFIG_SYS_I2C_MAC1_BUS 3 225 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 226 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 227 #define CONFIG_SYS_I2C_MAC2_BUS 0 228 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 229 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 230 231 #define CONFIG_RTC_MCP79411 1 232 #define CONFIG_SYS_RTC_BUS_NUM 3 233 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 234 235 /* 236 * eSPI - Enhanced SPI 237 */ 238 239 /* 240 * General PCI 241 * Memory space is mapped 1-1, but I/O space must start from 0. 242 */ 243 244 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 245 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 248 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 249 #else 250 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 251 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 252 #endif 253 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 254 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 255 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 256 #ifdef CONFIG_PHYS_64BIT 257 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 258 #else 259 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 260 #endif 261 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 262 263 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 264 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 265 #ifdef CONFIG_PHYS_64BIT 266 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 267 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 268 #else 269 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 270 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 271 #endif 272 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 273 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 274 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 277 #else 278 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 279 #endif 280 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 281 282 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 283 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 286 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 287 #else 288 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 289 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 290 #endif 291 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 292 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 293 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 296 #else 297 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 298 #endif 299 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 300 301 /* controller 4, Base address 203000 */ 302 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 303 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 304 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 305 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 306 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 307 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 308 309 /* Qman/Bman */ 310 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 311 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 312 #ifdef CONFIG_PHYS_64BIT 313 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 314 #else 315 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 316 #endif 317 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 318 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 319 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 320 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 321 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 322 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 323 CONFIG_SYS_BMAN_CENA_SIZE) 324 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 326 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 327 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 330 #else 331 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 332 #endif 333 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 334 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 335 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 336 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 337 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 338 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 339 CONFIG_SYS_QMAN_CENA_SIZE) 340 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 341 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 342 343 #define CONFIG_SYS_DPAA_FMAN 344 /* Default address of microcode for the Linux Fman driver */ 345 /* 346 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 347 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 348 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 349 */ 350 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 351 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 352 353 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 354 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 355 356 #ifdef CONFIG_SYS_DPAA_FMAN 357 #define CONFIG_FMAN_ENET 358 #endif 359 360 #ifdef CONFIG_PCI 361 #define CONFIG_PCI_INDIRECT_BRIDGE 362 363 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 364 #endif /* CONFIG_PCI */ 365 366 /* SATA */ 367 #ifdef CONFIG_FSL_SATA_V2 368 #define CONFIG_SYS_SATA_MAX_DEVICE 2 369 #define CONFIG_SATA1 370 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 371 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 372 #define CONFIG_SATA2 373 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 374 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 375 376 #define CONFIG_LBA48 377 #endif 378 379 #ifdef CONFIG_FMAN_ENET 380 #define CONFIG_SYS_TBIPA_VALUE 8 381 #define CONFIG_MII /* MII PHY management */ 382 #define CONFIG_ETHPRIME "FM1@DTSEC4" 383 #endif 384 385 /* 386 * Environment 387 */ 388 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 389 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 390 391 /* 392 * USB 393 */ 394 #define CONFIG_HAS_FSL_DR_USB 395 #define CONFIG_HAS_FSL_MPH_USB 396 397 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 398 #define CONFIG_USB_EHCI_FSL 399 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 400 #define CONFIG_EHCI_IS_TDI 401 /* _VIA_CONTROL_EP */ 402 #endif 403 404 #ifdef CONFIG_MMC 405 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 406 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 407 #endif 408 409 /* 410 * Miscellaneous configurable options 411 */ 412 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 413 414 /* 415 * For booting Linux, the board info and command line data 416 * have to be in the first 64 MB of memory, since this is 417 * the maximum mapped by the Linux kernel during initialization. 418 */ 419 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 420 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 421 422 #ifdef CONFIG_CMD_KGDB 423 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 424 #endif 425 426 /* 427 * Environment Configuration 428 */ 429 #define CONFIG_ROOTPATH "/opt/nfsroot" 430 #define CONFIG_BOOTFILE "uImage" 431 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 432 433 /* default location for tftp and bootm */ 434 #define CONFIG_LOADADDR 1000000 435 436 #define __USB_PHY_TYPE utmi 437 438 #define CONFIG_EXTRA_ENV_SETTINGS \ 439 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 440 "bank_intlv=cs0_cs1;" \ 441 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 442 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 443 "netdev=eth0\0" \ 444 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 445 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 446 "consoledev=ttyS0\0" \ 447 "ramdiskaddr=2000000\0" \ 448 "fdtaddr=1e00000\0" \ 449 "bdev=sda3\0" 450 451 #define CONFIG_HDBOOT \ 452 "setenv bootargs root=/dev/$bdev rw " \ 453 "console=$consoledev,$baudrate $othbootargs;" \ 454 "tftp $loadaddr $bootfile;" \ 455 "tftp $fdtaddr $fdtfile;" \ 456 "bootm $loadaddr - $fdtaddr" 457 458 #define CONFIG_NFSBOOTCOMMAND \ 459 "setenv bootargs root=/dev/nfs rw " \ 460 "nfsroot=$serverip:$rootpath " \ 461 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 462 "console=$consoledev,$baudrate $othbootargs;" \ 463 "tftp $loadaddr $bootfile;" \ 464 "tftp $fdtaddr $fdtfile;" \ 465 "bootm $loadaddr - $fdtaddr" 466 467 #define CONFIG_RAMBOOTCOMMAND \ 468 "setenv bootargs root=/dev/ram rw " \ 469 "console=$consoledev,$baudrate $othbootargs;" \ 470 "tftp $ramdiskaddr $ramdiskfile;" \ 471 "tftp $loadaddr $bootfile;" \ 472 "tftp $fdtaddr $fdtfile;" \ 473 "bootm $loadaddr $ramdiskaddr $fdtaddr" 474 475 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 476 477 #include <asm/fsl_secure_boot.h> 478 479 #ifdef CONFIG_SECURE_BOOT 480 #endif 481 482 #endif /* __CONFIG_H */ 483