1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_DISPLAY_BOARDINFO 11 12 #define CONFIG_CYRUS 13 14 #define CONFIG_PHYS_64BIT 15 16 #if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) 17 #error Must call Cyrus CONFIG with a specific CPU enabled. 18 #endif 19 20 #define CONFIG_MMC 21 #define CONFIG_SDCARD 22 #define CONFIG_FSL_SATA_V2 23 #define CONFIG_PCIE3 24 #define CONFIG_PCIE4 25 #ifdef CONFIG_PPC_P5020 26 #define CONFIG_SYS_FSL_RAID_ENGINE 27 #define CONFIG_SYS_DPAA_RMAN 28 #endif 29 #define CONFIG_SYS_DPAA_PME 30 31 /* 32 * Corenet DS style board configuration file 33 */ 34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 36 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 37 #if defined(CONFIG_PPC_P5020) 38 #define CONFIG_SYS_CLK_FREQ 133000000 39 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 40 #elif defined(CONFIG_PPC_P5040) 41 #define CONFIG_SYS_CLK_FREQ 100000000 42 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 43 #endif 44 45 /* High Level Configuration Options */ 46 #define CONFIG_BOOKE 47 #define CONFIG_E500 /* BOOKE e500 family */ 48 #define CONFIG_E500MC /* BOOKE e500mc family */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 #define CONFIG_MP /* support multiple processors */ 51 52 #define CONFIG_SYS_MMC_MAX_DEVICE 1 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xeff40000 56 #endif 57 58 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 59 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 60 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 61 #define CONFIG_PCI /* Enable PCI/PCIE */ 62 #define CONFIG_PCIE1 /* PCIE controller 1 */ 63 #define CONFIG_PCIE2 /* PCIE controller 2 */ 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 66 67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #define CONFIG_SYS_NO_FLASH 72 73 #if defined(CONFIG_SDCARD) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_ENV_IS_IN_MMC 76 #define CONFIG_FSL_FIXED_MMC_LOCATION 77 #define CONFIG_SYS_MMC_ENV_DEV 0 78 #define CONFIG_ENV_SIZE 0x2000 79 #define CONFIG_ENV_OFFSET (512 * 1658) 80 #endif 81 82 /* 83 * These can be toggled for performance analysis, otherwise use default. 84 */ 85 #define CONFIG_SYS_CACHE_STASHING 86 #define CONFIG_BACKSIDE_L2_CACHE 87 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 88 #define CONFIG_BTB /* toggle branch predition */ 89 #define CONFIG_DDR_ECC 90 #ifdef CONFIG_DDR_ECC 91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 92 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 93 #endif 94 95 #define CONFIG_ENABLE_36BIT_PHYS 96 97 #ifdef CONFIG_PHYS_64BIT 98 #define CONFIG_ADDR_MAP 99 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 100 #endif 101 102 /* test POST memory test */ 103 #undef CONFIG_POST 104 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 105 #define CONFIG_SYS_MEMTEST_END 0x00400000 106 #define CONFIG_SYS_ALT_MEMTEST 107 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 108 109 /* 110 * Config the L3 Cache as L3 SRAM 111 */ 112 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 115 #else 116 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 117 #endif 118 #define CONFIG_SYS_L3_SIZE (1024 << 10) 119 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 120 121 #ifdef CONFIG_PHYS_64BIT 122 #define CONFIG_SYS_DCSRBAR 0xf0000000 123 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 124 #endif 125 126 /* 127 * DDR Setup 128 */ 129 #define CONFIG_VERY_BIG_RAM 130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 132 133 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 134 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 135 136 #define CONFIG_DDR_SPD 137 #define CONFIG_SYS_FSL_DDR3 138 139 #define CONFIG_SYS_SPD_BUS_NUM 1 140 #define SPD_EEPROM_ADDRESS1 0x51 141 #define SPD_EEPROM_ADDRESS2 0x52 142 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 143 144 /* 145 * Local Bus Definitions 146 */ 147 148 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 151 #else 152 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 153 #endif 154 155 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 156 #ifdef CONFIG_PHYS_64BIT 157 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 158 #else 159 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 160 #endif 161 162 /* Set the local bus clock 1/16 of platform clock */ 163 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 164 165 #define CONFIG_SYS_BR0_PRELIM \ 166 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 167 #define CONFIG_SYS_BR1_PRELIM \ 168 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 169 170 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 171 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 172 173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 174 175 #if defined(CONFIG_RAMBOOT_PBL) 176 #define CONFIG_SYS_RAMBOOT 177 #endif 178 179 #define CONFIG_BOARD_EARLY_INIT_F 180 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 181 #define CONFIG_MISC_INIT_R 182 183 #define CONFIG_HWCONFIG 184 185 /* define to use L1 as initial stack */ 186 #define CONFIG_L1_INIT_RAM 187 #define CONFIG_SYS_INIT_RAM_LOCK 188 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 189 #ifdef CONFIG_PHYS_64BIT 190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 192 /* The assembler doesn't like typecast */ 193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 194 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 195 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 196 #else 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 200 #endif 201 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 202 203 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 205 206 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 207 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 208 209 /* Serial Port - controlled on board with jumper J8 210 * open - index 2 211 * shorted - index 1 212 */ 213 #define CONFIG_CONS_INDEX 1 214 #define CONFIG_SYS_NS16550_SERIAL 215 #define CONFIG_SYS_NS16550_REG_SIZE 1 216 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 217 218 #define CONFIG_SYS_BAUDRATE_TABLE \ 219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 220 221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 222 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 223 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 224 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 225 226 /* I2C */ 227 #define CONFIG_SYS_I2C 228 #define CONFIG_SYS_I2C_FSL 229 #define CONFIG_I2C_MULTI_BUS 230 #define CONFIG_I2C_CMD_TREE 231 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 232 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 233 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 234 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 235 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 236 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 237 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 238 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 239 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 240 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 241 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 243 244 #define CONFIG_ID_EEPROM 245 #define CONFIG_SYS_I2C_EEPROM_NXID 246 #define CONFIG_SYS_EEPROM_BUS_NUM 0 247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 249 250 #define CONFIG_SYS_I2C_GENERIC_MAC 251 #define CONFIG_SYS_I2C_MAC1_BUS 3 252 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 253 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 254 #define CONFIG_SYS_I2C_MAC2_BUS 0 255 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 256 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 257 258 #define CONFIG_CMD_DATE 1 259 #define CONFIG_RTC_MCP79411 1 260 #define CONFIG_SYS_RTC_BUS_NUM 3 261 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 262 263 /* 264 * eSPI - Enhanced SPI 265 */ 266 267 /* 268 * General PCI 269 * Memory space is mapped 1-1, but I/O space must start from 0. 270 */ 271 272 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 273 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 276 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 277 #else 278 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 279 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 280 #endif 281 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 282 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 283 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 286 #else 287 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 288 #endif 289 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 290 291 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 292 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 295 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 296 #else 297 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 298 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 299 #endif 300 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 301 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 302 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 303 #ifdef CONFIG_PHYS_64BIT 304 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 305 #else 306 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 307 #endif 308 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 309 310 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 311 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 312 #ifdef CONFIG_PHYS_64BIT 313 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 314 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 315 #else 316 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 317 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 318 #endif 319 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 320 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 321 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 324 #else 325 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 326 #endif 327 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 328 329 /* controller 4, Base address 203000 */ 330 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 331 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 332 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 333 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 334 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 335 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 336 337 /* Qman/Bman */ 338 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 339 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 340 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 341 #ifdef CONFIG_PHYS_64BIT 342 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 343 #else 344 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 345 #endif 346 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 347 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 348 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 349 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 350 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 351 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 352 CONFIG_SYS_BMAN_CENA_SIZE) 353 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 354 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 355 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 356 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 359 #else 360 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 361 #endif 362 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 363 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 364 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 365 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 366 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 367 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 368 CONFIG_SYS_QMAN_CENA_SIZE) 369 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 370 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 371 372 #define CONFIG_SYS_DPAA_FMAN 373 /* Default address of microcode for the Linux Fman driver */ 374 /* 375 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 376 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 377 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 378 */ 379 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 380 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 381 382 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 383 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 384 385 #ifdef CONFIG_SYS_DPAA_FMAN 386 #define CONFIG_FMAN_ENET 387 #define CONFIG_PHY_MICREL 388 #define CONFIG_PHY_MICREL_KSZ9021 389 #endif 390 391 #ifdef CONFIG_PCI 392 #define CONFIG_PCI_INDIRECT_BRIDGE 393 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 394 #define CONFIG_NET_MULTI 395 396 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 397 #define CONFIG_DOS_PARTITION 398 #endif /* CONFIG_PCI */ 399 400 /* SATA */ 401 #ifdef CONFIG_FSL_SATA_V2 402 #define CONFIG_LIBATA 403 #define CONFIG_FSL_SATA 404 405 #define CONFIG_SYS_SATA_MAX_DEVICE 2 406 #define CONFIG_SATA1 407 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 408 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 409 #define CONFIG_SATA2 410 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 411 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 412 413 #define CONFIG_LBA48 414 #define CONFIG_CMD_SATA 415 #define CONFIG_DOS_PARTITION 416 #endif 417 418 #ifdef CONFIG_FMAN_ENET 419 #define CONFIG_SYS_TBIPA_VALUE 8 420 #define CONFIG_MII /* MII PHY management */ 421 #define CONFIG_ETHPRIME "FM1@DTSEC4" 422 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 423 #endif 424 425 /* 426 * Environment 427 */ 428 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 429 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 430 431 /* 432 * Command line configuration. 433 */ 434 #define CONFIG_CMD_ERRATA 435 #define CONFIG_CMD_IRQ 436 #define CONFIG_CMD_REGINFO 437 438 #ifdef CONFIG_PCI 439 #define CONFIG_CMD_PCI 440 #endif 441 442 /* 443 * USB 444 */ 445 #define CONFIG_HAS_FSL_DR_USB 446 #define CONFIG_HAS_FSL_MPH_USB 447 448 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 449 #define CONFIG_USB_STORAGE 450 #define CONFIG_USB_EHCI 451 #define CONFIG_USB_EHCI_FSL 452 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 453 #define CONFIG_EHCI_IS_TDI 454 #define CONFIG_USB_KEYBOARD 455 #define CONFIG_SYS_STDIO_DEREGISTER 456 #define CONFIG_SYS_USB_EVENT_POLL 457 /* _VIA_CONTROL_EP */ 458 #define CONFIG_CONSOLE_MUX 459 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 460 #endif 461 462 #ifdef CONFIG_MMC 463 #define CONFIG_FSL_ESDHC 464 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 465 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 466 #define CONFIG_GENERIC_MMC 467 #define CONFIG_DOS_PARTITION 468 #endif 469 470 /* 471 * Miscellaneous configurable options 472 */ 473 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 474 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 475 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 476 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 477 #ifdef CONFIG_CMD_KGDB 478 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 479 #else 480 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 481 #endif 482 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 483 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 484 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 485 486 /* 487 * For booting Linux, the board info and command line data 488 * have to be in the first 64 MB of memory, since this is 489 * the maximum mapped by the Linux kernel during initialization. 490 */ 491 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 492 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 493 494 #ifdef CONFIG_CMD_KGDB 495 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 496 #endif 497 498 /* 499 * Environment Configuration 500 */ 501 #define CONFIG_ROOTPATH "/opt/nfsroot" 502 #define CONFIG_BOOTFILE "uImage" 503 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 504 505 /* default location for tftp and bootm */ 506 #define CONFIG_LOADADDR 1000000 507 508 509 #define CONFIG_BAUDRATE 115200 510 511 #define __USB_PHY_TYPE utmi 512 513 #define CONFIG_EXTRA_ENV_SETTINGS \ 514 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 515 "bank_intlv=cs0_cs1;" \ 516 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 517 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 518 "netdev=eth0\0" \ 519 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 520 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 521 "consoledev=ttyS0\0" \ 522 "ramdiskaddr=2000000\0" \ 523 "fdtaddr=1e00000\0" \ 524 "bdev=sda3\0" 525 526 #define CONFIG_HDBOOT \ 527 "setenv bootargs root=/dev/$bdev rw " \ 528 "console=$consoledev,$baudrate $othbootargs;" \ 529 "tftp $loadaddr $bootfile;" \ 530 "tftp $fdtaddr $fdtfile;" \ 531 "bootm $loadaddr - $fdtaddr" 532 533 #define CONFIG_NFSBOOTCOMMAND \ 534 "setenv bootargs root=/dev/nfs rw " \ 535 "nfsroot=$serverip:$rootpath " \ 536 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 537 "console=$consoledev,$baudrate $othbootargs;" \ 538 "tftp $loadaddr $bootfile;" \ 539 "tftp $fdtaddr $fdtfile;" \ 540 "bootm $loadaddr - $fdtaddr" 541 542 #define CONFIG_RAMBOOTCOMMAND \ 543 "setenv bootargs root=/dev/ram rw " \ 544 "console=$consoledev,$baudrate $othbootargs;" \ 545 "tftp $ramdiskaddr $ramdiskfile;" \ 546 "tftp $loadaddr $bootfile;" \ 547 "tftp $fdtaddr $fdtfile;" \ 548 "bootm $loadaddr $ramdiskaddr $fdtaddr" 549 550 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 551 552 #include <asm/fsl_secure_boot.h> 553 554 #ifdef CONFIG_SECURE_BOOT 555 #endif 556 557 #endif /* __CONFIG_H */ 558